DS1992/DS1993

14of 14

Figure 10. INITIALIZATION PROCEDURE RESET AND PRESENCE PULSE

RESISTOR

MASTER

DS199X

MASTER RX "PRESENCE PULSE"

MASTER TX

"RESET PULSE"

0V

* In order not to mask interrup signaling

** Includes recovery time

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line

low initiates all time slots. The falling edge of the data line synchronizes the DS199_ to the master by

triggering a delay circuit in the DS199_. During write time slots, the delay circuit determines when the

DS199_ samples the data line. For a read data time slot, if a 0 is to be transmitted, the delay circuit

determines how long the DS199_ holds the data line low overriding the 1 generated by the master. If the

data bit is a 1, the iButton leaves the read data time slot unchanged.

Figure 11. READ/WRITE TIMING DIAGRAM

Write-One Time Slot

15µs

60µs

DS199X

Sampling Window

0V

60 µs

1 µs

RESISTOR

MASTER