2x4-Channel, Simultaneous-Sampling

12-Bit ADCs

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5

CONDITIONS

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

TIMING CHARACTERISTICS (continued)

unless otherwise noted.)

µs

2

4

6

8

Exiting shutdown

ms

20

Startup Time

Note 1:

Note 2:

Integral nonlinearity is the analog value’s deviation at any code from its theoretical value after the full-scale range and

offset have been calibrated.

Note 3:

CLK synchronized with CONVST.

Note 4:

Note 5:

First five harmonics.

Note 6:

All inputs except CH1A driven with ±5V (MAX115) or ±2.5V (MAX116) 10.06kHz signal, CH1A connected to AGND and digi-

tized.

Note 7:

Note 8:

TC = [

∆REFOUT/REFOUT] / ∆T.

Note 9:

See Figure 2.

Note 10: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage. Tested with one input

Note 12: The data access time is defined as the time required for an output to cross +0.8V or +2.0V. It is measured using the circuit

of Figure 1. The measured number is then extrapolated back to determine the value with a 25pF load.

Note 13: The bus relinquish time is derived from the measured time taken for the data outputs to change +0.5V when loaded with the

circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging and discharging the

120pF capacitor. The time given is the part’s true bus relinquish time, which is independent of the external bus loading capac-

itance.

Conversion Time

ksps

390

Conversion Rate

218

152

116