WM8756 datasheet(15/39 Pages) WOLFSON

15 / 39 page

WM8756

Advance Information

AI Rev 1.3 October 2001

2S MODE

In I

2S mode, the MSB is sampled on the second rising edge of BCKIN following a LRCIN transition.

LRCIN is low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN0/1/2

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCKIN

Figure 8 I

2S Mode Timing Diagram

DSP EARLY MODE

In DSP early mode, the first bit is sampled on the BCKIN edge following the one which detects a low to

high transition on LRCIN.

1 BCKIN

LRCIN

BCKIN

DIN0

Input Word Length (IWL)

1/fs

CHANNEL 0

LEFT

n-1

LSB

MSB

n-1

CHANNEL 0

RIGHT

CHANNEL 1

LEFT

n-1

CHANNEL 2

RIGHT

NO VALID DATA

1 BCKIN

Figure 9 DSP Early Mode Timing Diagram

DSP LATE MODE

In DSP late mode, the first bit is sampled on the BCKIN edge which detects a low to high transition on

LRCIN.

LRCIN

BCKIN

DIN0

Input Word Length (IWL)

1/fs

CHANNEL 0

LEFT

n-1

LSB

MSB

n-1

CHANNEL 0

RIGHT

CHANNEL 1

LEFT

n-1

CHANNEL 2

RIGHT

NO VALID DATA

Figure 10 DSP Late Mode Timing Diagram

In both early and late DSP modes, DAC0 left is always sent first, followed immediately by data words for

the other 5 channels. No BCKIN edges are allowed between the data words. The word order is DAC0 left,

DAC0 right, DAC1 left, DAC1 right, DAC2 left, DAC2 right.

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