WM8756

Advance Information

AI Rev 1.3 October 2001

37

CXD2753R

WM8756

BCKAO

PHREFO

DSAL

DSAR

DSDCLK128

DSDCLK64

DSD1

DSD0

DSD3

DSD2

DSD5

DSD4

DSAC

DSASW

DSALS

DSARS

Figure 34 Connection of WM8756 as Slave to Sony 6-CH DSD Decoder Chip in Normal mode

To use the WM8756 with the Sony CXD2753R there are several configuration options:

1.

In DSD mode if the WM8756 is being run in NORMAL mode as a SLAVE device the only clock input which the WM8756

requires is DSDCLK64, this should be connected to the BCKAO pin of the CXD2753R. In this BCKAO should be a falling

edge set as illustrated on page 20 of the CXD2753R datasheet (Rev PE01704-PS).

2.

In DSD mode if the WM8756 is being run in PHASE MODULATION mode as a SLAVE device the clock inputs which the

WM8756 requires are DSDCLK64 and DSDCLK128. DSDCLK64 and DSDCLK128 should be connected to PHREFO and

BCKAO respectively on the CXD2753R. In Phase Modulation mode phase 2 should be selected for the PHREFO clock

and BCKAO should be a rising edge set, as illustrated on page 20 of the CXD2753R datasheet (Rev PE01704-PS).

−

To run the WM8756 in DSD mode but as a MASTER SCLK must be present on the device.

−

If the device is intended to be used for both PCM and DSD data in either MASTER or SLAVE mode SCLK can be present

on the WM8756 at all times as this pin is ignored by the WM8756 when it is not required.