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ICS952607 Datasheet(PDF) 1 Page - Integrated Circuit Systems

Part # ICS952607
Description  Programmable Timing Control Hub for Next Gen P4 processor
PDF  21 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS952607 Datasheet(HTML) 1 Page - Integrated Circuit Systems

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Integrated
Circuit
Systems, Inc.
ICS952607
Advance Information
0734—07/16/04
Pin Configuration
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
2 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
9 - PCI, 3 free running, 33MHz
3 - REF, 14.318MHz
3 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
2 - 48MHz
1 - 24/48MHz
Key Specifications:
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Programmable Timing Control Hub™ for Next Gen P4™ processor
Functionality
Features/Benefits:
QuadRom
TM frequency selection.
Programmable output frequency.
Programmable asynchronous 3V66&PCI frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system
malfunctions.
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
Uses external 14.318MHz reference input.
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
Supports CPU clks up to 400MHz
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
48-pin SSOP
Bit4 Bit3 Bit2 Bit1 Bit0
CPU
AGP
PCI
FS4FS3 FS2FS1 FS0
MHz
MHz
MHz
000
00
100.00
66.66
33.33
000
01
200.00
66.66
33.33
000
10
133.33
66.66
33.33
000
11
166.67
66.66
33.33
0
0
1
0
0
200.00
66.66
33.33
001
01
400.00
66.66
33.33
001
10
266.67
66.66
33.33
001
11
333.33
66.66
33.33
010
00
100.99
67.33
33.66
010
01
201.98
67.33
33.66
010
10
134.65
67.33
33.66
010
11
168.31
67.32
33.66
01
1
00
115.00
76.66
38.33
011
01
230.00
76.66
38.33
011
10
153.33
76.66
38.33
011
11
191.67
76.66
38.33
1
00
00
100.00
66.66
33.33
100
01
200.00
66.66
33.33
100
10
133.33
66.66
33.33
100
11
166.67
71.43
35.71
1
0
1
0
0
200.00
66.66
33.33
101
01
400.00
66.66
33.33
101
10
266.67
66.66
33.33
101
11
333.33
66.66
33.33
110
00
105.00
69.99
35.00
110
01
210.00
69.99
35.00
110
10
140.00
69.99
35.00
110
11
175.00
69.99
35.00
11
1
00
110.00
73.33
36.66
111
01
220.00
73.33
36.66
111
10
146.66
73.33
36.66
111
11
183.34
73.33
36.66
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
*FS1/REF0
1
48 VDDA
*FS0/REF1
2
47 GND
REF2
3
46 IREF
VDDREF
4
45 Reset#
X1
5
44 GND
X2
6
43 CPUCLKT1
GND
7
42 CPUCLKC1
**FS2/PCICLK_F0
8
41 VDDCPU
**FS4/PCICLK_F1
9
40 CPUCLKT0
PCICLK_F2 10
39 CPUCLKC0
VDDPCI 11
38 GND
GND 12
37 SRCCLKT
^^PCICLK0 13
36 SRCCLKC
PCICLK1 14
35 VDD
PCICLK2 15
34 VttPWR_GD/PD#
PCICLK3 16
33 SDATA
VDDPCI 17
32 SCLK
GND 18
31 3V66_0
PCICLK4 19
30 3V66_1
PCICLK5 20
29 GND
**Sel24_48#/24_48MHz 21
28 VDD3V66
**FS3/48MHz_0 22
27 3V66_2
48MHz_1 23
26 3V66_3/VCH
GND 24
25 VDD48
^^ An external 2.2K pull-down resistor is needed on this pin
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND


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