UDA1380 datasheet(30/68 Pages) ICST

30 / 68 page

2002 Sep 16

Philips Semiconductors

Product speciﬁcation

Stereo audio coder-decoder

for MD, CD and MP3

UDA1380

11.1

Evaluation modes and clock settings

Table 17 Register address 00H

Table 18 Description of register bits

BIT

Symbol

EV2

EV1

EV0

−

EN_ADC

EN_DEC

EN_DAC

EN_INT

Default

BIT

Symbol

−−

ADC_CLK

DAC_CLK

sys_div1

sys_div0

PLL1

PLL0

Default

BIT

SYMBOL

DESCRIPTION

15 to 13

EV[2:0]

Evaluation bits. Bits EV2, EV1 and EV0 are special control bits for

manufacturer’s evaluation and must always be kept at their default values for

normal operation of UDA1380; default value 000, see Table 17.

−

default value 0

EN_ADC

ADC clock enable. A 1-bit value to enable the system clock (from SYSCLK

input) to the analog part of the ADC. See Fig.5 for more detailed information.

When this bit is logic 0: clock to ADC disabled and when this bit is logic 1: clock

to ADC running. Default value 0.

EN_DEC

Decimator clock enable. A 1-bit value to enable the 128fs clock to the

decimator, the 128fs part of the I2S-bus output block and the clock to the ADC

L3-bus or I2C-bus registers. See Fig.5 for more detailed information. When this

bit is logic 0: clock to the decimator disabled. When this bit is logic 1: clock to

the decimator running. Default value 1.

EN_DAC

FSDAC clock enable. A 1-bit value to enable the 256fs clock to the analog part

of the FSDAC. See Fig.5 for more detailed information. When this bit is logic 0:

clock to FSDAC disabled. When this bit is logic 1: clock to the FSDAC running.

Default value 0.

EN_INT

Interpolator clock enable. A 1-bit value to enable the 128fs clock to the

interpolator, the 128fs part of the I2S-bus input block and the interpolator

registers of the L3-bus or I2C-bus interface. See Fig.5 for more detailed

information. When this bit is logic 0: clock to the interpolator disabled. When

this bit is logic 1: clock to the interpolator running. Default value 1.

7 and 6

−

default value 00

ADC_CLK

ADC clock select. A 1-bit value to select the 128fs clock and the clock of the

analog part for the decimator and the ADC. This can either be the clock derived

from the SYSCLK input or from the WSPLL. When this bit is logic 0: SYSCLK

is used. When this bit is logic 1: WSPLL is used. Default value 0.

UDA1380 Datasheet(PDF) 30 Page - Integrated Circuit Systems

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