UDA1380 datasheet(39/68 Pages) ICST

39 / 68 page

2002 Sep 16

Philips Semiconductors

Product speciﬁcation

Stereo audio coder-decoder

for MD, CD and MP3

UDA1380

11.8

Mode, bass boost and treble

Table 38 Register address 12H

Table 39 Description of register bits

Table 40 Flat/minimum/maximum setting bits

11100100

−∞

:::::::::

11111100

−∞

BIT

Symbol

TRL1

TRL0

BBL3

BBL2

BBL1

BBL0

Default

BIT

76543210

Symbol

−−

TRR1

TRR0

BBR3

BBR2

BBR1

BBR0

Default

BIT

SYMBOL

DESCRIPTION

15 and 14

M[1:0]

Flat/minimum/maximum setting. A 2-bit value to program the mode of the sound

processing ﬁlters of bass boost and treble. Default value 00, see Table 40.

13 and 12

TRL[1:0]

Treble setting left. A 2-bit value to program the mode of the sound processing ﬁlter of

treble. The used setting depends on the bits M1 and M0. Default value 00, see Table 41.

11 to 8

BBL[3:0]

Bass boost setting left. A 4-bit value to program the bass boost setting, which can be set

for left and right independently. The used set depends on the bits M1 and M0. Default

value 0000, see Table 42.

7 and 6

−

default value 00

5 and 4

TRR[1:0]

Treble setting right. A 2-bit value to program the mode of the sound processing ﬁlter of

treble. Default value 00, see Table 41.

3 to 0

BBR[3:0]

Bass boost setting right. A 4-bit value to program the bass boost setting, which can be

set for left and right independently. The used set depends on the mode bits. Default

value 0000, see Table 42.

MODE

ﬂat (default)

minimum

maximum

VC2_7

VC1_7

VC2_6

VC1_6

VC2_5

VC1_5

VC2_4

VC1_4

VC2_3

VC1_3

VC2_2

VC1_2

VC2_1

VC1_1

VC2_0

VC1_0

VOLUME

(dB)

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