LM9833 datasheet(20/42 Pages) NSC

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MISC I/O 5: Input or Output

0 The MISC I/O 5 pin is configured as an input.

1 The MISC I/O 5 pin is configured as an output.

MISC I/O 5: Polarity

(if configured as an input)

A low input on MISC I/O 5 is True

A high input on MISC I/O 5 is True

MISC I/O 5: Level/Edge sensitive

(if configured as an input)

Level sensitive: MISC I/O 5 State bit (in Status

Edge sensitive: MISC I/O 5 State bit (in Status

since the last time the Status Register was read.

MISC I/O 5: Output State

(if configured as an output)

Power On/USB Suspend Default: Output,

Logic High

The output of the MISC I/O 5 pin will be a logic low

(0V).

The output of the MISC I/O 5 pin will be a logic high

(5V).

MISC I/O 6: Input or Output

The MISC I/O 6 pin is configured as an input.

The MISC I/O 6 pin is configured as an output.

MISC I/O 6: Polarity

(if configured as an input)

A low input on MISC I/O 6 is True

A high input on MISC I/O 6 is True

MISC I/O 6: Level/Edge sensitive

(if configured as an input)

Level sensitive: MISC I/O 6 State bit (in Status

Edge sensitive: MISC I/O 6 State bit (in Status

since the last time the Status Register was read.

MISC I/O 6: Output State

(if configured as an output)

Power On/USB Suspend Default: Output,

Logic Low

The output of the MISC I/O 6 pin will be a logic low

(0V).

The output of the MISC I/O 6 pin will be a logic high

(5V).

TEST MODE SETTINGS

ADC Output Code - MSB

n nnnnnnnUsed to force the input to the HDPI Divider to a known

value for digital tests

ADC Output Code - LSB

n nnnnnnn

ADC Test Mode

0 0 Normal Operation

0 1 Bypass AFE, Normal ADC Operation

Bypass AFE, bypass ADC digital correction,

output uncorrected ADC MSB

Bypass AFE, bypass ADC digital correction,

output uncorrected ADC LSB

Pixel Processing Input Select

0 0

Normal Operation - ADC Output

0 1

Registers 5C and 5D

1 0

16 bit counter, reset at the start of every scan

1 1

16 bit counter, reset at the start of every line

16 bit Counter Increment Select

(16 bit counter starts at 0, increments every

datapixel)

0 0

Increments by 1

0 1

Increments by 4

1 0

Increments by 16

N/A

MCLK edge for AFE (Set this bit to 0)

Rising

Falling

CDS Signal

Normal Operation

CDS signal is output on LAMPB pin

5F-68

Reserved

0 0000000Write 00 to these registers

Version Number

100

100 = LM9832 or LM9833

(011 = LM9831, 010 = LM9830)

6A-7F

Reserved

0 0000000Write 00 to these registers

Address

Function

Value

LM9833 Datasheet(PDF) 20 Page - National Semiconductor (TI)

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