TFP410

TI PanelBus DIGITAL TRANSMITTER

SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

7

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

dc specifications

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High le el inp t oltage (CMOS inp t)

VREF = DVDD

0.7 VDD

V

VIH

High-level input voltage (CMOS input)

0.5 V

 VREF  0.95 V

VREF + 0.2

V

V

Lo

le el inp t oltage (CMOS inp t)

VREF = DVDD

0.3VDD

V

VIL

Low-level input voltage (CMOS input)

0.5 V

 VREF  0.95 V

VREF – 0.2

V

VOH

High-level digital output voltage (open-drain output)

VDD = 3 V, IOH = 20 µA

2.4

V

VOL

Low-level digital output voltage (open-drain output)

VDD = 3.6 V, IOL = 4 mA

0.4

V

IIH

High-level input current

VI = 3.6 V

±25

µA

IIL

Low-level input current

VI = 0

±25

µA

VH

DVI single-ended high-level output voltage

AVDD – 0.01

AVDD + 0.01

V

VL

DVI single-ended low-level output voltage

AVDD = 3.3 V ± 5%,

RT† 50 Ω ± 10%

AVDD – 0.6

AVDD – 0.4

V

DVI single-ended output swing voltage

RT† = 50 Ω ± 10%,

RTFADJ = 510 Ω ± 1%

400

600

mVP-P

VOFF

DVI single-ended standby/off output voltage

RTFADJ = 510 Ω ± 1%

AVDD – 0.01

AVDD + 0.01

V

IPD

Power-down current (see Note 3)

200

500

µA

IIDD

Normal power supply current

Worst case pattern‡

200

250

mA

† RT is the single-ended termination resistance at the receiver end of the DVI link.

‡ Black and white checkerboard pattern, each checker is one pixel wide.

NOTE 3: Assumes all inputs to the transmitter are not toggling.

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(IDCK)

IDCK frequency

25

165

MHz

t(pixel)

Pixel time period (see Note 4)

6.06

40

ns

t(IDCK)

IDCK duty cycle

30%

70%

t(ijit)

IDCK clock jitter tolerance

2

ns

tr

DVI output rise time (20-80%) (see Note5)

75

240

ps

tf

DVI output fall time (20-80%) (see Note 5)

75

240

ps

tsk(D)

DVI output intra-pair + to – differential skew (see Note 6)

f(IDCK) = 165 MHz

50

ps

tsk(CC)

DVI output inter-pair or channel-to-channel skew (see Note 6)

f(IDCK) 165 MHz

1.2

ns

tojit

DVI output clock jitter, max. (see Note 7)

150

ps

tsu(IDF)

Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge

Single edge

(BSEL 1 DSEL 0

1.2

ns

th(IDF)

Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge

(BSEL=1, DSEL=0,

DKEN=0, EDGE=0)

1.3

ns

tsu(IDR)

Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge

Single edge

(BSEL 1 DSEL 0

1.2

ns

th(IDR)

Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge

(BSEL=1, DSEL=0,

DKEN=0, EDGE=1)

1.3

ns

tsu(ID)

Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising

edge

Dual edge

(BSEL=0, DSEL=1,

DKEN=0)

0.9

ns

th(ID)

Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising

edge

Dual edge (BSEL=0,

DSEL=1, DKEN=0)

1

ns

t(STEP)

De-skew trim increment

DKEN = 1

350

ps

NOTES:

4. t(pixel) is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t(pixel).

5. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.

6. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.

7. Relative to input clock (IDCK).