1

9

1

9

Ack

by

Device

Start by

Master

SCL

SDA

R/W

0

1

A0

1

0

A1

Ack

by

Device

Frame 1

Serial Bus Address

Byte from Master

Frame 2

Pointer Byte

from Master

P7 P6 P5 P4 P3 P2 P1 P0

0

Stop

by

Master

13

TMP468

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SBOS762 – NOVEMBER 2016

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Copyright © 2016, Texas Instruments Incorporated

8.5 Programming

8.5.1 Serial Interface

made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike suppression

filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP468 supports the

transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 2.56 MHz) modes. All data bytes are

transmitted MSB first.

While the TMP468 is unpowered bus traffic on SDA and SCL may continue without any adverse effects to the

communication or to the TMP468. As the TMP468 is powering up, it will not load the bus, thus bus traffic may

continue undisturbed.

8.5.1.1 Bus Overview

initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be

controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the

start and stop conditions.

To address a specific device, a start condition is initiated. A start condition is indicated by pulling the data line

(SDA) from a high-to-low logic level when SCL is high. All slaves on the bus shift in the slave address byte, with

the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being

addressed responds to the master by generating an acknowledge (Ack) bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit (Ack). During data

transfer, SDA must remain stable when SCL is high. A change in SDA when SCL is high is interpreted as a

control signal. The TMP468 has a word register structure (16-bits wide) thus data writes must always include 2

bytes. Data transfer occurs during the Ack at the end of the second byte.

After all data are transferred, the master generates a stop condition. A stop condition is indicated by pulling SDA

from low to high when SCL is high.

8.5.1.2 Bus Definitions

for various operations on the TMP468. The bus definitions are as follows:

Bus Idle:

Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line (from high to low) when the SCL line is high defines

a start condition. Each data transfer initiates with a start condition.

Stop Data Transfer: A change in the state of the SDA line (from low to high) when the SCL line is high defines

a stop condition. Each data transfer terminates with a repeated start or stop condition.

Data Transfer: The number of data bytes transferred between a start and stop condition is not limited and is

determined by the master device. The receiver acknowledges the data transfer.

Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge bit. A device

that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way

that the SDA line is stable low during the high period of the acknowledge clock pulse. Take setup

and hold times into account. On a master receive, data transfer termination can be signaled by the

master generating a not-acknowledge on the last byte that is transmitted by the slave.

Figure 16. Two-Wire Timing Diagram for Write Pointer Byte