PCI7421 datasheet(180/298 Pages) TI

180 / 298 page

7−20

Table 7−23. GPIO Control Register Description (Continued)

BIT

SIGNAL

TYPE

FUNCTION

GPIO_ENB1

R/W

GPIO1 enable control. When bit 15 (DISABLE_LPS) is set to 1, this bit controls the output enable for

GPIO1.

0 = High-impedance output (default)

1 = Output is enabled

11−9

RSVD

Reserved. Bits 11−9 return 0s when read.

GPIO_DATA1

R/W

GPIO1 data. When bit 15 (DISABLE_LPS) is set to 1 and GPIO1 output is enabled, the value written to

this bit represents the logical data driven to the GPIO1 terminal.

DISABLE_BMC

R/W

Disable bus manager contender (BMC). This bit configures this terminal as bus manager contender or

GPIO0.

0 = BMC (default)

1 = GPIO0

RSVD

Reserved. Bit 6 returns 0 when read.

GPIO_INV0

R/W

GPIO0 polarity invert. When bit 7 (DISABLE_BMC) is set to 1, this bit controls the input/output polarity

control for GPIO0.

0 = Noninverted (default)

1 = Inverted

GPIO_ENB0

R/W

GPIO0 enable control. When bit 7 (DISABLE_BMC) is set to 1, this bit controls the output enable for

GPIO0.

0 = High-impedance output (default)

1 = Output is enabled

3−1

RSVD

Reserved. Bits 3−1 return 0s when read.

GPIO_DATA0

R/W

GPIO0 data. When bit 7 (DISABLE_BMC) is set to 1 and GPIO0 output is enabled, the value written to

this bit represents the logical data driven to the GPIO0 terminal.

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