PCI7421 datasheet(181/298 Pages) TI

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8−1

8 OHCI Registers

The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a

2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see

Section 7.8). These registers are the primary interface for controlling the PCI7x21/PCI7x11 IEEE 1394 link function.

This section provides the register interface and bit descriptions. Several set/clear register pairs in this programming

model are implemented to solve various issues with typical read-modify-write control registers. There are two

addresses for a set/clear register: RegisterSet and RegisterClear. See Table 8−1 for a register listing. A 1 bit written

to RegisterSet causes the corresponding bit in the set/clear register to be set to 1; a 0 bit leaves the corresponding

bit unaffected. A 1 bit written to RegisterClear causes the corresponding bit in the set/clear register to be cleared;

a 0 bit leaves the corresponding bit in the set/clear register unaffected.

Typically, a read from either RegisterSet or RegisterClear returns the contents of the set or clear register, respectively.

However, sometimes reading the RegisterClear provides a masked version of the set or clear register. The interrupt

event register is an example of this behavior.

Table 8−1. OHCI Register Map

DMA CONTEXT

ABBREVIATION

OFFSET

—

OHCI version

Version

00h

GUID ROM

GUID_ROM

04h

Asynchronous transmit retries

ATRetries

08h

CSR data

CSRData

0Ch

CSR compare

CSRCompareData

10h

CSR control

CSRControl

14h

Configuration ROM header

ConfigROMhdr

18h

Bus identification

BusID

1Ch

Bus options ‡

BusOptions

20h

GUID high ‡

GUIDHi

24h

GUID low ‡

GUIDLo

28h

Reserved

—

2Ch−30h

Configuration ROM mapping

ConfigROMmap

34h

Posted write address low

PostedWriteAddressLo

38h

Posted write address high

PostedWriteAddressHi

3Ch

Vendor ID

VendorID

40h

Reserved

—

44h−4Ch

Host controller control ‡

HCControlSet

50h

Host controller control ‡

HCControlClr

54h

Reserved

—

58h−5Ch

‡ One or more bits in this register are cleared only by the assertion of GRST.

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