PCI7421 datasheet(198/298 Pages) TI

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8−18

8.21 Interrupt Event Register

The interrupt event set/clear register reflects the state of the various PCI7x21/PCI7x11 interrupt sources. The

interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the

corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the

corresponding bit in the clear register.

This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the PCI7x21/PCI7x11

controller adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the return value

is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 8−15 for a complete

description of the register contents.

Bit

Name

Interrupt event

Type

RSC

RSCU

Default

Bit

Name

Interrupt event

Type

RSCU

Default

Interrupt event

Offset:

80h

set register

84h

clear register [returns the content of the interrupt event register bit-wise ANDed with

the interrupt mask register when read]

Type:

Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read-only

Default:

XXXX 0XXXh

Table 8−15. Interrupt Event Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31−30

RSVD

Reserved. Bits 31 and 30 return 0 when read.

SoftInterrupt

RSC

Bit 29 is used by software to generate a PCI7x21/PCI7x11 interrupt for its own use.

RSVD

Reserved. Bit 28 returns 0 when read.

ack_tardy

RSCU

Bit 27 is set to 1 when bit 29 (AckTardyEnable) in the host controller control register at OHCI offset

50h/54h (see Section 8.16) is set to 1 and any of the following conditions occur:

a. Data is present in a receive FIFO that is to be delivered to the host.

b. The physical response unit is busy processing requests or sending responses.

c. The PCI7x21/PCI7x11 controller sent an ack_tardy acknowledgment.

phyRegRcvd

RSCU

The PCI7x21/PCI7x11 controller has received a PHY register data byte which can be read from bits

23−16 in the PHY layer control register at OHCI offset ECh (see Section 8.33).

cycleTooLong

RSCU

If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 8.31) is set to

1, then this indicates that over 125

µs has elapsed between the start of sending a cycle start packet

and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is cleared by this event.

unrecoverableError

RSCU

This event occurs when the PCI7x21/PCI7x11 controller encounters any error that forces it to stop

operations on any or all of its subunits, for example, when a DMA context sets its dead bit to 1. While

bit 24 is set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked from

being set to 1.

cycleInconsistent

RSCU

A cycle start was received that had values for the cycleSeconds and cycleCount fields that are

different from the values in bits 31−25 (cycleSeconds field) and bits 24−12 (cycleCount field) in the

isochronous cycle timer register at OHCI offset F0h (see Section 8.34).

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