PCI7421 datasheet(199/298 Pages) TI

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8−19

Table 8−15. Interrupt Event Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

cycleLost

RSCU

A lost cycle is indicated when no cycle_start packet is sent or received between two successive

cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately

follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after

a cycleSynch event without an intervening cycle start. Bit 22 may be set to 1 either when a lost cycle

occurs or when logic predicts that one will occur.

cycle64Seconds

RSCU

Indicates that the seventh bit of the cycle second counter has changed.

cycleSynch

RSCU

Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low-order bit of the

cycle count toggles.

phy

RSCU

Indicates that the PHY layer requests an interrupt through a status transfer.

regAccessFail

RSCU

Indicates that a PCI7x21/PCI7x11 register access has failed due to a missing SCLK clock signal from

the PHY layer. When a register access fails, bit 18 is set to 1 before the next register access.

busReset

RSCU

Indicates that the PHY layer has entered bus reset mode.

selfIDcomplete

RSCU

A self-ID packet stream has been received. It is generated at the end of the bus initialization process.

Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.

selfIDcomplete2

RSCU

Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1 by the PCI7x21/PCI7x11

controller when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset).

14−10

RSVD

Reserved. Bits 14−10 return 0s when read.

lockRespErr

RSCU

Indicates that the PCI7x21/PCI7x11 controller sent a lock response for a lock request to a serial bus

postedWriteErr

RSCU

Indicates that a host bus error occurred while the PCI7x21/PCI7x11 controller was trying to write a

1394 write request, which had already been given an ack_complete, into system memory.

isochRx

Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have

generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous

receive interrupt event register at OHCI offset A0h/A4h (see Section 8.25) and isochronous receive

interrupt mask register at OHCI offset A8h/ACh (see Section 8.26). The isochronous receive interrupt

event register indicates which contexts have been interrupted.

isochTx

Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have

generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous

transmit interrupt event register at OHCI offset 90h/94h (see Section 8.23) and isochronous transmit

interrupt mask register at OHCI offset 98h/9Ch (see Section 8.24). The isochronous transmit

interrupt event register indicates which contexts have been interrupted.

RSPkt

RSCU

Indicates that a packet was sent to an asynchronous receive response context buffer and the

descriptor xferStatus and resCount fields have been updated.

RQPkt

RSCU

Indicates that a packet was sent to an asynchronous receive request context buffer and the

descriptor xferStatus and resCount fields have been updated.

ARRS

RSCU

Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1 upon completion of an

ARRS DMA context command descriptor.

ARRQ

RSCU

Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1 upon completion of an

ARRQ DMA context command descriptor.

respTxComplete

RSCU

Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1 upon completion of an

ATRS DMA command.

reqTxComplete

RSCU

Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1 upon completion of an

ATRQ DMA command.

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