PCI7421 datasheet(208/298 Pages) TI

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8−28

8.31 Link Control Register

The link control set/clear register provides the control flags that enable and configure the link core protocol portions

of the PCI7x21/PCI7x11 controller. It contains controls for the receiver and cycle timer. See Table 8−23 for a complete

description of the register contents.

Bit

Name

Link control

Type

RSC

RSCU

RSC

Default

Bit

Name

Link control

Type

RSC

Default

Link control

Offset:

E0h

set register

E4h

clear register

Type:

Read/Set/Clear/Update, Read/Set/Clear, Read-only

Default:

00X0 0X00h

Table 8−23. Link Control Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31−23

RSVD

Reserved. Bits 31−23 return 0s when read.

cycleSource

RSC

When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to roll

over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches

3072 cycles of the 24.576-MHz clock (125

µs).

cycleMaster

RSCU

When bit 21 is set to 1, the PCI7x21/PCI7x11 controller is root and it generates a cycle start packet

every time the cycle timer rolls over, based on the setting of bit 22 (cycleSource). When bit 21 is

cleared, the OHCI-Lynx

 accepts received cycle start packets to maintain synchronization with the

node which is sending them. Bit 21 is automatically cleared when bit 25 (cycleTooLong) in the

interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1. Bit 21 cannot be set to

1 until bit 25 (cycleTooLong) is cleared.

CycleTimerEnable

RSC

When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over

at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle

timer offset does not count.

19−11

RSVD

Reserved. Bits 19−11 return 0s when read.

RcvPhyPkt

RSC

When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if

the AR request context is enabled. This bit does not control receipt of self-identification packets.

RcvSelfID

RSC

When bit 9 is set to 1, the receiver accepts incoming self-identification packets. Before setting this

bit to 1, software must ensure that the self-ID buffer pointer register contains a valid address.

8−7

RSVD

Reserved. Bits 8 and 7 return 0s when read.

6 ‡

tag1SyncFilterLock

When bit 6 is set to 1, bit 6 (tag1SyncFilter) in the isochronous receive context match register (see

Section 8.46) is set to 1 for all isochronous receive contexts. When bit 6 is cleared, bit 6

(tag1SyncFilter) in the isochronous receive context match register has read/write access. This bit is

cleared when GRST is asserted.

5−0

RSVD

Reserved. Bits 5−0 return 0s when read.

‡ This bit is cleared only by the assertion of GRST.

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