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PCI7421 Datasheet(PDF) 209 Page - Texas Instruments |
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PCI7421 Datasheet(HTML) 209 Page - Texas Instruments |
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209 / 298 page ![]() 8−29 8.32 Node Identification Register The node identification register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See Table 8−24 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Node identification Type RU RU R R RU R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Node identification Type RWU RWU RWU RWU RWU RWU RWU RWU RWU RWU RU RU RU RU RU RU Default 1 1 1 1 1 1 1 1 1 1 X X X X X X Register: Node identification Offset: E8h Type: Read/Write/Update, Read/Update, Read-only Default: 0000 FFXXh Table 8−24. Node Identification Register Description BIT FIELD NAME TYPE DESCRIPTION 31 iDValid RU Bit 31 indicates whether or not the PCI7x21/PCI7x11 controller has a valid node number. It is cleared when a 1394 bus reset is detected and set to 1 when the PCI7x21/PCI7x11 controller receives a new node number from its PHY layer. 30 root RU Bit 30 is set to 1 during the bus reset process if the attached PHY layer is root. 29−28 RSVD R Reserved. Bits 29 and 28 return 0s when read. 27 CPS RU Bit 27 is set to 1 if the PHY layer is reporting that cable power status is OK. 26−16 RSVD R Reserved. Bits 26−16 return 0s when read. 15−6 busNumber RWU This field identifies the specific 1394 bus the PCI7x21/PCI7x11 controller belongs to when multiple 1394-compatible buses are connected via a bridge. The default value for this field is all 1s. 5−0 NodeNumber RU This field is the physical node number established by the PHY layer during self-identification. It is automatically set to the value received from the PHY layer after the self-identification phase. If the PHY layer sets the nodeNumber to 63, then software must not set bit 15 (run) in the asynchronous context control register (see Section 8.40) for either of the AT DMA contexts. |
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