PCI7421 datasheet(228/298 Pages) TI

228 / 298 page

9−4

9.4

Link Enhancement Register

This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI

offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM,

if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must

be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see

Section 8.16). See Table 9−3 for a complete description of the register contents.

Bit

Name

Link enhancement

Type

Default

Bit

Name

Link enhancement

Type

RSC

Default

Link enhancement

Offset:

A88h

set register

A8Ch

clear register

Type:

Read/Set/Clear, Read-only

Default:

0000 0000h

Table 9−3. Link Enhancement Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31−16

RSVD

Reserved. Bits 31−16 return 0s when read.

15 ‡

dis_at_pipeline

Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled. The default value for this

bit is 0.

14 ‡

RSVD

Reserved. Bit 14 defaults to 0 and must remain 0 for normal operation of the OHCI core.

13−12

‡

atx_thresh

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

PCI7x21/PCI7x11 controller retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward

operation.

00 = Threshold ~ 2K bytes resulting in a store-and-forward operation

01 = Threshold ~ 1.7K bytes (default)

10 = Threshold ~ 1K bytes

11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is

optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus

latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or

when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT

threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun

condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences a

store-and-forward operation. It waits until it has the complete packet in the FIFO before retransmitting it on

the second attempt to ensure delivery.

An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is not

transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only

complete packets being transmitted.

Note that this controller always uses a store-and-forward operation when the asynchronous transmit retries

RSVD

Reserved. Bit 11 returns 0 when read.

10 ‡

enab_mpeg_ts

Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled for MPEG

CIP transmit streams (FMT = 20h). The default value for this bit is 0.

‡ This bit is cleared only by the assertion of GRST.

PCI7421 Datasheet(PDF) 228 Page - Texas Instruments

PCI7421 Datasheet(HTML) 228 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL