PCI7421 datasheet(229/298 Pages) TI

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9−5

Table 9−3. Link Enhancement Register Description (Continued)

BIT

FIELD NAME

TYPE

DESCRIPTION

RSVD

Reserved. Bit 9 returns 0 when read.

8 ‡

enab_dv_ts

Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV

CIP transmit streams (FMT = 00h). The default value for this bit is 0.

7 ‡

enab_unfair

Enable asynchronous priority requests. OHCI-Lynx

 compatible. Setting bit 7 to 1 enables the link to

respond to requests with priority arbitration. It is recommended that this bit be set to 1. The default value

for this bit is 0.

RSVD

This bit is not assigned in the PCI7x21/PCI7x11 follow-on products, because this bit location loaded

by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the

host controller control register at OHCI offset 50h/54h (see Section 8.16).

5−3

RSVD

Reserved. Bits 5−3 return 0s when read.

2 ‡

RSVD

Reserved. Bit 2 returns 0 when read.

1 ‡

enab_accel

Enable acceleration enhancements. OHCI-Lynx

 compatible. When bit 1 is set to 1, the PHY layer

is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,

ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1. The default value

for this bit is 0.

RSVD

Reserved. Bit 0 returns 0 when read.

‡ This bit is cleared only by the assertion of GRST.

9.5

Timestamp Offset Register

The value of this register is added as an offset to the cycle timer value when using the MPEG, DV, and CIP

enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following

the offset indicates the context number (n = 0, 1, 2, 3,

…, 7). These registers are programmed by software as

appropriate. See Table 9−4 for a complete description of the register contents.

Bit

Name

Timestamp offset

Type

Default

Bit

Name

Timestamp offset

Type

Default

Timestamp offset

Offset:

A90h + (4*n)

Type:

Read/Write, Read-only

Default:

0000 0000h

Table 9−4. Timestamp Offset Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

DisableInitialOffset

Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are enabled.

A value of 0 indicates the use of the initial offset, a value of 1 indicates that the initial offset must not

be applied to the calculated timestamp. This bit has no meaning for the DV timestamp

enhancements. The default value for this bit is 0.

30−25

RSVD

Reserved. Bits 30−25 return 0s when read.

24−12

CycleCount

This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2

enhancements are enabled. The cycle count field is incremented modulo 8000; therefore, values in

this field must be limited between 0 and 7999. The default value for this field is all 0s.

11−0

CycleOffset

This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2

enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore, values in

this field must be limited between 0 and 3071. The default value for this field is all 0s.

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