MPT57481

240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS

SGLS099 – MARCH 1997

6

POST OFFICE BOX 655303

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

CLK

I

Shift Clock. CLK synchronizes internal control logic with its rising edge. Also, CLK generates a data clock

for the Data Latch, a shift clock for the Address Shift Register, and a write enable for the Storage Register.

D00-D05

D10-D15

D20-D25

I

Data Input. Data inputs consist of 6-bit words for each of three channels (18 bits) for color input data.

EIO1

Enable I/O. EIO enables the Data Latch and Input Register to load 18-bit RGB data into the input Register

on the rising edge of the clocks. The cascade output is for adding additional drivers to extend the length of

line data. This helps to accommodate any particular LCD panel being driven.

EIO1

EIO2

I/O

L/R = is asserted

L/R is deasserted

EIO1

Right-shift input

Left-shift output

EIO2

Right-shift output

Left-shift input

GMA1...GMA9

I

Analog circuit bias voltage. GMA supplies the bias voltage to the DAC and the gamma correction voltage

adjust reference voltage.

L/R

I

Shift Direction. L/R controls the direction in which the data is loaded into the input register. The data is loaded

from OUT1 to OUT240 when L/R is asserted and from OUT240 to OUT1 when L/R is deasserted.

OUT1-OUT240

O

Subpixel output. Out provides 64 gray-scale signals to the LCD panel.

TP1, TP2

I

Transfer input register contents. The next CLK rising edge after TP1 is deasserted causes the contents of

the input register (line n-1) to be transferred to the storage register (line n). After the transfer, the input

register receives new line n–1 data from the data inputs. During the period that either TP1, TP2, or both are

deasserted, pixel-driver output is in a precharge mode that supplies voltage to all the OUT terminals (LCD

pixel drivers)

VDD1

I

Analog supply voltage. The four VDD1 terminals supply power for the analog circuitry.

VDD2

I

Power supply for digital circuitry.

VOP

I

Bias voltage. VOP supplies the bias voltage for each DAC.

VSS1

I

Analog circuit ground.

VSS2

I

Digital circuit ground.

WB0, WB1,

WB2

I

Reference voltages. WB0, WB1, WB2 are reference voltages for each third DAC and RGB shift voltage

adjust.