MPT57481

240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS

SGLS099 – MARCH 1997

8

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIH

High level input voltage

Dx0 – Dx5, CLK, TP1,

TP2, EIO1, EIO2

2.2

V

VIH

High level in ut voltage

L/R

0.7 VDD2

V

VIL

Low level input voltage

Dx0 – Dx5, CLK, TP1,

TP2, EIO1, EIO2

0.8

V

VIL

Low level in ut voltage

L/R

0.3 VDD2

V

IIK

Input leakage current

Dx0 – Dx5, CLK, TP1,

TP2, EIO1, EIO2, L/R

–10

10

µA

IO(1)

TP1, TP2 = 0 V,

VO = 4 V

–1.5

IO(2)

Output current

OUT1 – 240

TP1, TP2 = 5 V,

Dx5 – Dx0 = 00h

VO = 4 V,

–10

mA

IO(3)

TP1, TP2 = 5 V,

Dx5 – Dx0 = 63h

VO = 4 V,

0.8

VO

Subpixel output error

(see Note 4)

OUT1 – 240

±30

mV

VO

Subpixel output voltage

range (see Note 5)

OUT1 – 240

VSS1 + 0.2

VDD1– 0.2

V

VDD1

Hsync = 30

µs,

No load

9

IDD

Supply current

VDD1

Hsync = 30

µs,

See Note 6

5

mA

VDD2

Hsync = 30

µs,

No load

5

† All typical values are at VDD1, VDD2 = 5 V and TA = 25°C.

NOTES:

3. For this table, the following are true: GMA1 – GMA9 = 0.5 V to 4.5 V in increments of 0.5 V, VOP = 2.5 V and WB0 – WB2 = 2.5 V.

4. VO is the difference between the highest and the lowest reading across OUT1 – OUT240.

5. This is the range of output voltage between 6-bit input data 00h and 63h.

6. The load consists of a 75-pF capacitor connected from the output to VSS and in parallel with a series combination of a 75-pF capacitor

and a 2-k

Ω resistor.