MPT57481

240-CHANNEL 61-BIT SOURCE DRIVER FOR COLOR TFT LCDS

SGLS099 – MARCH 1997

9

POST OFFICE BOX 655303

See Note 7

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tc1

Clock cycle time

See Figure 3

18

ns

tw1

High-level pulse width duration

See Figure 3

5

ns

tw2

Low-level pulse width duration

See Figure 3

5

ns

tsu1

Data setup time

See Figure 3, Figure 4, and Figure 5

5

ns

th1

Data hold time

See Figure 3, Figure 4, and Figure 5

5

ns

tsu2

Start pulse setup time

See Figure 3 and Figure 4

5

ns

th2

Start pulse hold time

See Figure 3 and Figure 4

5

ns

tsu3

Enable propagation setup time

See Figure 3

80

CLK

t(pc)

Precharge time

See Figure 3

3

µs

th3

TP1 hold time (with respect to TP2)

See Figure 3

1

µs

tsu4

TP1 setup time (with respect to TP2)

See Figure 3

1

µs

th4

TP2 hold time (with respect to TP1)

See Figure 3

0.5

µs

tsu5

TP1 shift input setup time

See Figure 3

1

CLK

tdis1

Data input disable time

See Figure 4

1

CLK

t(last)

Last data timing

See Figure 5

1

CLK

tsu6

TP1 setup time (with respect to CLK)

See Figure 5

7

ns

th5

TP1, CLK hold time (with respect to CLK)

See Figure 5

7

ns

NOTE 7: All VIH and VIL input voltage levels are 5 V and 0 V, respectively.

5 V, See Figure 3 and Note 7

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td1

Enable propagation delay time

CL = 35 pF

11

ns

td2

Enable propagation delay time

CL = 35 pF

15

ns

td3

Output propagation delay time

CL1. CL2= 75 pF,

See Note 6

RL = 2 kΩ,

3

ns

td4

Output propagation delay time

CL1. CL2= 75 pF,

See Note 6

RL = 2 kΩ,

10

ns

NOTES:

6. The load consists of a 75-pF capacitor connected from the output to VSS and in parallel with a series combination of a 75-pF capacitor

and a 2-k

Ω resistor.

7. All VIH and VIL input voltage levels are 5 V and 0 V, respectively.