YMF721 datasheet(7/41 Pages) LSI

7 / 41 page

YMF721

July 10, 1997

- 7 -

(2) No ISA BUS Connect System

Note :

YMF721 (OPL4-ML2) has MPU401 UART in it. Thus, for the above case, TXD of YMF7xx (OPL3-SAx)

is connected with RXD of YMF721 (OPL4-ML2) and MPU401 port (/MPUCS) of YMF721 (OPL4-ML2)

is disabled so that YMF7xx(OPL3-SAx) sends MIDI data directly to YMF721 (OPL4-ML2).

The above system does not connect YMF721 (OPL4-ML2) and ISA bus, which is an example of Wavetable

upgrade solution represented by the Wavetable daughter card. Input pins of the ISA bus interface should be

pulled up externally. At this time, FM synthesizer/Command/Control ports are disabled, but the power

down function is enabled by receiving System Exclusive Message on the MIDI data, except that

Suspend/Resume function is disabled.

As a source of master clock for YMF721 (OPL4-ML2), use a crystal oscillator by connecting it to XI and

XO pins, or use the clock of 33.8688 MHz from the system. Connect BCO, LRO, DO2, /PDOUT and

CLKO directly to YAC516 (DAC16-L) as shown to convert serial data output to analog signal. Then, it is

recommended to input the converted analog signal to AUX2L and AUX2R of YMF7xx (OPL3-SAx) after

amplifying the volume of source of YMF721 through the gain of +12 dB as shown for the purpose of

equalizing the volumes of multiple sources.

YMF7xx

(OPL3-SAx)

RESET

TXD

Lch

AUX2L

Rch

AUX2R

LRCK

MCLK

/PDIN

BCLK

SDATA

ARDY

RST

A2-0

/IOW

/IOR

ADB7-0

ABDIR

/OPLCS

/MPUCS

FSP

RXD

/PDOUT

CLKO

BCO

LRO

DO2

YMF721 Datasheet(PDF) 7 Page - LSI Computer Systems

YMF721 Datasheet(HTML) 7 Page - LSI Computer Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

Datasheet Download

Link URL