YMF721 datasheet(19/41 Pages) LSI

Part #	YMF721

Description	FM Wavetable Synthesizer LSI

PDF	41 Pages

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Manufacturer	LSI [LSI Computer Systems]

Direct Link	http://www.lsicsi.com

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19 / 41 page

YMF721

July 10, 1997

- 19 -

Data Register Array 1 (R/W)

Index

00 - 01h

LSI TEST

04h

CONNECTION SEL

05h

NEW3

NEW2

NEW

20 - 35h

VIB

EGT

KSR

MULT

40 - 55h

KSL

60 - 75h

80 - 95h

A0 - A8h

F-NUM (L)

B0 - B8h

KON

BLOCK

F-NUM (H)

C0 - C8h

CHD

CHC

CHB

CHA

CNT

E0 - F5h

---

Default :

After initial clear, all the bits of Register Array 1 are cleared to "0" except NEW2 and NEW3 bits of

index 05h, and CHA and CHB bits of index C0-C8h.

For the details of these registers, refer to data sheet for YMF289B(OPL3-L).

Note :

Since NEW2 and 3 (at index 05h of Register array1) = 1 in default state, both LD and BUSY0 bits

are valid. (LD and BUSY0 bits are invalid when NEW2=0.) BUSY0 is a BUSY flag for both FM

and Wavetable registers.

YMF721 Datasheet(PDF) 19 Page - LSI Computer Systems

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