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YMF721 Datasheet(PDF) 9 Page - LSI Computer Systems |
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YMF721 Datasheet(HTML) 9 Page - LSI Computer Systems |
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9 / 41 page  YMF721 July 10, 1997 - 9 - 2. ISA bus interface 8 bit parallel I/O of YMF721 (OPL4-ML2) can be connected with ISA bus. The ISA bus interface allows transfer of commands between the each block of YMF721 (OPL4-ML2) and host. Data Bus & Address Bus ADB7-0 : ISA data bus A2-0 : ISA address bus /MPUCS : MPU401 chip select /OPLCS : FM/Wavetable/Command/Control chip select /IOW : ISA write enable /IOR : ISA read enable ABDIR : Data bus direction switching (“L” : YMF721 ® ISA) ARDY : I/O channel ready (“L” : busy) Control of the data bus is made with /MPUCS, /OPLCS, /IOW and /IOR signals. The mode of control of the data bus varies as follows according to the combination of states of the signals. The direction of data transfer on the data bus is determined by ABDIR. In normal operation, the internal data bus of YMF721 (OPL4-ML2) connects the built-in processor and FM/Wavetable synthesizer blocks. Every time the ISA bus accesses the register for FM/Wavetable, an internal arbitration circuit causes the internal bus to connect ISA bus and FM/Wavetable synthesizer blocks. YMF721 (OPL4-ML2) uses I/O channel ready (ARDY pin) as the internal arbitration circuit. ARDY becomes "L" (busy) every time data bus accesses the register for FM/Wavetable. /MPUCS /OPLCS /IOW /IOR A2 A1 A0 MODE LH H L ´ L L MPU401 Acknowledge (FEh) LH LH ´ L L MPU401 MIDI Data write LH H L ´ L H MPU401 Status read LH LH ´ L H MPU401 Command write H L H LLLL FM-synth. Status read H L L H L H/L L FM-synth. Address write HL L H L ´ H FM-synth. Data write HL HL L ´ H FM-synth. Data read H L H L H L L Wavetable-synth. Status read H L L H H L L Wavetable-synth. Address write H L L H H L H Wavetable-synth. Data write H L H L H L H Wavetable-synth. Data read HL HL H H L Command response read H L L HHH L Command write H L L HHHH Control write H L H L H H H Status read HL H H ´´´ No-active or UART mode HH ´´´´´ No-active or UART mode |
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