YMF721 datasheet(11/41 Pages) LSI

11 / 41 page

YMF721

July 10, 1997

- 11 -

4. MIDI Interface

MIDI serial data can be inputted from RXD pin. It is necessary to input MIDI data complied with MIDI

1.0 detailed specification to RXD pin.

The serial data is the rate of 31.25kbit/sec (+/-1%) and the unit of 10 bits. The first bit is a start bit, the

next 8 bits are data (LSB to MSB), and the 10th bit is a stop bit.

5. Power management functions

YMF721 (OPL4-ML2) has two types of power management functions as follows.

(1) Global power down mode

(2) Suspend/Resume mode

5-1. Global power down mode

Generation of clock signal is disabled (stopped). Total power consumption of YMF721 (OPL4-ML2) is

approximately 20uA (typ.). Writing "FDh" into command register or receiving System Exclusive MIDI

Message makes in this mode. YMF721 (OPL4-ML2) outputs "L" from /PDOUT pin in this mode,

which can be used as power down control signal for peripheral equipment. Set KON bit (FM

synthesizer register) to "0" for all channels before going into this mode. Check that play back of MIDI

data is stopped.

/RESETSEL pin has a built-in pull up resistor. When this pin is at "L" in this mode, the power

consumption is higher by approximately 30uA than the one when this pin is open or at "H".

5-1-1. ISA BUS Connect System

When "FDh" has been written into command register, the internal processor goes into the global power

down mode after performing the following internal processes.

1) Disabling synthesizer's internal clock

2) Setting GBUSY bit of status register to "0".

YMF721 (OPL4-ML2) requires over 30 msec to complete the above processes before going into the

power down mode.

Since generation of the clock has been disabled, recovery from the power down mode can not be made

by using command. Thus, it is necessary to use PDY and PDX bits of control register for the recovery.

To resume normal operation through the recovery sequence, waiting time of 50 to 100 msec is required

before the oscillation of crystal stabilizes when internal oscillation is used, or 3 msec or more before

the recovery of clock generated in the synthesizer.

For the details of power down command, refer to 6-3. After the power down command, FDh, has been

written, do not write any command before sending a recovery command to the control register to return

to the normal mode.

YMF721 Datasheet(PDF) 11 Page - LSI Computer Systems