ML610408 datasheet(13/34 Pages) LAPIS

13 / 34 page

FEDL610409-08

ML610407/ML610408/ML610409

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PIN DESCRIPTION

Pin name

I/O

Description

Primary/

Secondary/

Tertiary

Logic

System

RESET_N

Reset input pin. When this pin is set to a “L” level, system reset

mode is set and the internal section is initialized. When this pin is

set to a “H” level subsequently, program execution starts. A pull-up

resistor is internally connected.

—

Negative

XT0

—

XT1

Crystal connection pin for low-speed clock.

A 32.768 kHz crystal resonator is connected to this pin. Capacitors

CDL and CGL are connected across this pin and VSS. (see appendix

C measuring circuit 1)

—

LSCLK

O Low-speed clock output. Assigned to the secondary function of the

P20 pin.

Secondary

—

OUTCLK

O High-speed clock output pin. This pin is used as the secondary

function of the P21 pin.

Secondary

—

General-purpose input port

P00 to P04

General-purpose input port.

Primary

Positive

General-purpose output port

P20 to P22,

P24

O General-purpose output port.

This cannot be used as the general output port when used as the

secondary function.

Primary

Positive

General-purpose input/output port

P30 to P35

I/O General-purpose input/output port.

This cannot be used as the general input/output port when used as

the secondary function.

Primary

Positive

P40 to P47

I/O General-purpose input/output port.

This cannot be used as the general input/output port when used as

the secondary or tertiary function.

Primary

Positive

P50 to P57

I/O General-purpose input/output port.

This cannot be used as the general input/output port when used as

the secondary function.

Primary

Positive

P60 to P63

O General-purpose output port.

Incorporated only into ML610407/8, and not into ML610409.

Primary

Positive

P64 to P67

O General-purpose output port.

Incorporated only into ML610407, and not into ML610408/

ML610409.

Primary

Positive

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