FEDL610409-08

ML610407/ML610408/ML610409

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BLOCK DIAGRAM

ML610407/ML610408/ML610409 Block Diagram

*

Secondary function or Tertiary function

“*1”: Select among 29 segments x 5 commons, 30 segments x 4 commons, 31 segments x 3 commons, and 32 segments x 2

commons with the register

“*2”: Select among 33 segments x 5 commons, 34 segments x 4 commons, 35 segments x 3 commons, and 36 segments x 2

commons with the register

“*3”: Select among 37 segments x 5 commons, 38 segments x 4 commons, 39 segments x 3 commons, and 40 segments x 2

commons with the register

Figure 1 ML610413P Block Diagram

Program

Memory

(maskROM)

16Kbyte

RAM

1Kbyte

Interrupt

Controller

CPU (nX-U8/100)

Timing

Controller

EA

SP

On-Chip

ICE

Instruction

Decoder

BUS

Controller

Instruction

Register

TBC

INT

4

INT

1

WDT

INT

4

8bit Timer

x4

Capture

x2

GPIO

INT

6

Data-bus

Melody/

Buzzer

INT

1

MD0*

TEST0

RESET_N

OSC

XT0**

XT1**

LSCLK*

OUTCLK*

Power

LCD

Driver

LCD

BIAS

C1, C2

RC-ADC

x2

CS0*

IN0*

RS0*

RT0*

RCT0*

RCM*

CS1*

IN1*

RS1*

RT1*

RESET &

TEST

ALU

EPSW1-3

PSW

ELR1-3

LR

ECSR1-3

DSR/CSR

PC

GREG

0-15

INT

1

Display

register

320bit

Display

Allocation

RAM

COM0 to COM4 (*1)(*2)(*3)

SEG0 to SEG31 (ML610407) (*1)

SEG0 to SEG35 (ML610408) (*2)

SEG0 to SEG39 (ML610409) (*3)

P00 to P04

P20 to P22, P24

P30 to P35

P40 to P47

P50 to P53

P60 to P67 (ML610407)

P60 to P63 (ML610408)

SSIO

x2

SCK0*

SIN0*

SOUT0*

INT

2

SCK1*

SIN1*

SOUT1*

UART

INT

1

INT

1

PWM

RXD0*

TXD0*

PWM0*