FEDL9488-01

ML9488

6/31

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I

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Applicable pin

SCL clock frequency

—

—

400

kHz

SCL

Hold time (repeat)

"STATRT" condition

0.6

—

—

μs

SCL,SDA

SCL "L" pulse width

1.3

—

—

μs

SCL

SCL "H" pulse width

0.6

—

—

μs

SCL

Setup time for repeat

"START" condition

0.6

—

—

μs

SCL,SDA

Data hold time

0

—

—

ns

SCL,SDA

Data setup time

200

—

—

ns

SCL,SDA

Setup time for "STOP"

condition

0.6

—

—

μs

SCL,SDA

Bus free time between

"STOP" condition and

"START" condition

1.3

—

—

μs

SCL

Data valid acknowledge

time

—

—

1.2

μs

SCL,SDAAACK

Signal rise and fall time

tir,tif

—

—

(*3)

μs

 SCL,SDA

Data bus load

capacitance

Cb

—

—

400

pF

SDA,SDAACK

Noise pulse width

tolerance

—

—

50

ns

SCL,SDA

(*3) tir and tif shall be reference values.

The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.

Make the rise as steep as possible.

Reference value: max=0.1μs.