L3GD20HTR datasheet(19/52 Pages) STMICROELECTRONICS

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L3GD20H

Digital main blocks

FIFO_SRC(OVRN) is equal to '1' if a FIFO slot is overwritten.

FIFO feature is enabled writing to '1' CTRL5(FIFO_EN).

To guarantee the switching into and out of FIFO mode discard the first sample aquired.

4.2.1

Bypass mode

In bypass mode (FIFO_CTRL(FM2:0) = 000), the FIFO is not operational and it remains

empty.

Bypass mode is also used to reset the FIFO when in FIFO-mode.

As described in the next figure, for each channel only the first address is used. When a new

data is available the old one is overwritten.

Figure 7. Bypass mode

4.2.2

FIFO mode

In FIFO mode (FIFO_CTRL(FM2:0) = 001)

data from Yaw, Pitch and Roll channels are

stored into the FIFO until it is full.

To reset FIFO content Bypass mode should be written in FIFO_CTRL(FM2:0) '000' value.

After this reset command it is possible to restart FIFO mode writing FIFO_CTRL(FM2:0) the

value '001'.

FIFO buffer can memorize 32 Yaw, Pitch and Roll data, but the depth of the FIFO can be

reduced by means of CTRL5(StopOnFTH) bit setting to '1' StopOnFTH bit, FIFO depth is

limited to FIFO_CTRL(FTH4:0) - 1.

A FIFO Threshold interrupt can be enabled (INT2_ORun bit into CTRL3 (22h)) in order to be

raised when the FIFO is filled to the level specified into the FTH4:0 bits of FIFO_CTRL

(2Eh). When FIFO Threshold interrupt occurs, the first data has been overwritten and the

FIFO stops collecting data from the input channels.

L3GD20HTR Datasheet(PDF) 19 Page - STMicroelectronics