L3GD20HTR datasheet(24/52 Pages) STMICROELECTRONICS

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L3GD20H

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DocID023469 Rev 2

4.2.6

Bypass-to-FIFO mode

In bypass-to-FIFO mode (FIFO_CTRL(FM2:0) = '111', FIFO behavior changes according to

IG_SRC(IA) bit. When IG_SRC(IA) bit is equal to '1' FIFO operates in FIFO-mode, when

IG_SRC(IA) bit is equal to '0' FIFO operates in bypass mode (FIFO content reset). If a

latched interrupt is generated FIFO starts collecting data until the first data into the FIFO-

buffer is overwritten. Interrupt generator

should be set to the desired configuration by

means of IG_CFG, IG_THS_XH, IG_THS_XL, IG_THS_YH, IG_THS_YL, IG_THS_ZH and

IG_THS_ZL.

IG_CFG (LIR) bit should be put to '1' in order to have latched interrupt.

4.2.7

Retrieve data from FIFO

FIFO data is read through OUT_X_L and OUT_X_H (Addr reg 28h and 29h), OUT_Y_L

OUT_Y_H (Addr reg 2Ah and 2Bh) and OUT_Z_L and OUT_Z_H (Addr reg 2Ch and 2Dh)

registers. A read operation by means of serial interface of OUT_X, OUT_Y or OUT_Z output

registers provides the data stored into the FIFO. Each time data is read from the FIFO, the

oldest X, Y and Z data are placed into the OUT_X, OUT_Y and OUT_Z registers and both

single read and read_burst operations can be used.

4.2.8

FIFO multiple read (burst)

Starting from the Addr 28h multiple read can be performed. Once the reading reaches the

Addr 2Dh the system automatically restarts from the Addr. 28h.

Figure 14. FIFO multiple read

x,y,z

OUT_Z

Read #1

(2A-2B)

(2C-2D)

OUT_Y

(28-29)

OUT_X

x,y,z

Read #n

OUT_Z

(2A-2B)

(2C-2D)

OUT_Y

(28-29)

OUT_X

GAMS290120131638FSR

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