| Electronic Components Datasheet Search |
|
L3GD20HTR Datasheet(PDF) 48 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L3GD20HTR Datasheet(HTML) 48 Page - STMicroelectronics |
|
48 / 52 page ![]() Register description L3GD20H 48/52 DocID023469 Rev 2 7.24 LOW_ODR (39h) Table 62. LOW_ODR register -- -- DRDY_HL 0 (1) 1. These bits must be set to ‘0’ for proper working of the device. I2C_dis SW_RES 0 (1) Low_ODR Table 63. LOW_ODR description DRDY_HL DRDY/INT2 pin active level. Default value: 0 0 = DRDY active high 1 = DRDY active low I2C_dis 0 = both the I2C and SPI interfaces enabled (default) 1 = SPI only SW_RES Software reset. Default value: 0 0 = Normal Mode 1 = Reset Device (this bit is cleared by hardware after next flash boot) Low_ODR Low speed ODR. Default value: 0 Refer to Table 21 DR and BW configuration setting: for ODR and Bandwidth configuration on CTRL1 register 0 = Low Speed ODR disabled 1 = Low Speed ODR enabled |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |