LM5166 datasheet(41/53 Pages) TI1

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LM5166

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SNVSA67A – DECEMBER 2016 – REVISED DECEMBER 2016

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9 Power Supply Recommendations

The LM5166 is designed to operate from an input voltage supply range between 3 V and 65 V. This input supply

should be able to withstand the maximum input current and maintain a voltage above 3 V. Ensure that the

resistance of the input supply rail is low enough that an input current transient does not cause a high enough

drop at the LM5166 supply voltage to cause a false UVLO fault triggering and system reset. If the input supply is

located more than a few inches from the LM5166 converter, additional bulk capacitance may be required in

addition to the ceramic bypass capacitors. A 10-μF electrolytic capacitor is a typical choice for this function,

whereby the capacitor ESR provides a level of damping against input filter resonances. A typical ESR of 0.5 Ω

provides enough damping for most input circuit configurations.

10 PCB Layout

The performance of any switching converter depends as much upon PCB layout as it does the component

selection. The following guidelines are provided to assist with designing a PCB with the best power conversion

performance, thermal performance, and minimized generation of unwanted EMI.

10.1 PCB Layout Guidelines

PCB layout is a critical portion of good power supply design. There are several paths that conduct high slew-rate

currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or

degrade the power supply performance.

1. To help eliminate these problems, bypass the VIN pin to GND with a low ESR ceramic bypass capacitor with

a high-quality dielectric. Place CIN as close as possible to the LM5166 VIN and GND pins. Grounding for

both the input and output capacitors should consist of localized top-side planes that connect to the GND pin

and GND PAD.

2. Minimize the loop area formed by the input filter capacitor connections to the VIN and GND pins.

3. Locate the filter inductor close to the SW pin. Minimize the area of the SW trace/plane to prevent excessive

capacitive coupling.

4. Tie the GND pin directly to the power pad under the device and to a heat-sinking PCB ground plane.

5. Use a ground plane in one of the middle layers as noise shielding and heat dissipation path.

6. Have a single-point ground connection to the plane. Route the ground connections for the feedback, soft-

start, and enable components to the ground plane. This prevents any switched or load currents from flowing

in analog ground traces. If not properly handled, poor grounding results in degraded load regulation or erratic

output voltage ripple behavior.

7. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on the

input or output paths of the converter and maximizes efficiency.

8. Minimize trace length to the FB pin. Locate both feedback resistors, RFB1 and RFB2 close to the FB pin. Place

CFF (if needed) directly in parallel with RFB1. If output setpoint accuracy at the load is important, connect the

VOUT sense at the load. Route the VOUT sense path away from noisy nodes and preferably through a layer on

the other side of a shielding layer.

9. The RT pin is sensitive to noise. Thus, locate the RRT resistors as close as possible to the device and route

with minimal lengths of trace. The parasitic capacitance from RT to GND must not exceed 20 pF.

10. Provide adequate heat-sinking for the LM5166 to keep the junction temperature below 150°C. For operation

at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-

sinking vias to connect the exposed pad to the PCB ground plane. If the PCB has multiple copper layers,

these thermal vias should also be connected to inner layer heat-spreading ground planes.

10.1.1 Compact PCB Layout for EMI Reduction

Radiated EMI generated by high di/dt components relates to pulsing currents in switching converters. The larger

area covered by the path of a pulsing current, the more electromagnetic emission is generated. The key to

minimize radiated EMI is to identify the pulsing current path and minimize the area of that path.

The critical switching loop of the power stage in terms of EMI is denoted in Figure 82. The topological

architecture of a buck converter means that a particularly high di/dt current path exists in the loop comprising the

input capacitor and the LM5166's integrated MOSFETs, and it becomes mandatory to reduce the parasitic

inductance of this loop by minimizing the effective loop area.

LM5166 Datasheet(PDF) 41 Page - Texas Instruments

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