PC87311AVF datasheet(48/78 Pages) NSC

48 / 78 page

50 FDC Functional Description

(Continued)

Specify command values will be don’t cares so they must

be reinitialized The major default conditions are FIFO dis-

abled FIFO threshold e 0 Implied Seeks disabled and

Drive Polling enabled

A software reset can be performed through the Digital Out-

put Register or Data Rate Select Register The DSR reset

bit is self-clearing while the DOR reset bit is not self-clear-

ing If the LOCK bit in the Lock command was set to a 1

previous to the software reset the FIFO THRESH and

PRETRK parameters in the Configure command will be re-

tained In addition the FWR FRD and BST parameters in

the Mode command will be retained if LOCK is set to 1 This

function eliminates the need for total reinitialization of the

controller after a software reset

After a hardware (assuming the FDC is enabled in the FER)

or software reset the Main Status Register is immediately

available for read access by the mP It will return a 00 hex

value until all the internal registers have been updated and

the data separator is stabilized When the controller is ready

to receive a command byte the MSR will return a value of

80 hex (Request for Master bit is set) The MSR is guaran-

teed to return the 80 hex value within 25 ms after a hard-

ware or software reset All other user addressable registers

other than the Main Status Register and Data Register

(FIFO) can be accessed at any time even while the part is

in reset

60 Serial Ports

61 INTRODUCTION

Each of these serial ports functions as a serial data input

output interface in a microcomputer system The system

software determines the functional configuration of the

UARTs via a 8-bit bidirectional data bus

The UARTs are completely independent They perform seri-

al-to-parallel conversion on data characters received from a

peripheral device or a MODEM and parallel-to-serial con-

version on data characters received from the CPU The

CPU can read the complete status of either UART at any

time during the functional operation Status information re-

ported includes the type and condition of the transfer opera-

tions being performed by the UART as well as any error

conditions (parity overrun framing or break interrupt)

The UARTs have programmable baud rate generators that

are capable of dividing the internal reference clock by divi-

sors of 1 to (2

16 – 1) and producing a 16 x clock for driv-

ing the transmitter logic Provisions are also included to use

this 16 x clock to drive the receiver logic The UARTs have

complete MODEM-control capability and a prioritized inter-

rupt system Interrupts can be programmed to the user’s

requirements minimizing the computing required to handle

the communications link

The PC87311A UARTs can operate in the INS8250-B mode

(XT) or the NS16450 mode (AT) depending on the state of

the XTSEL pin during reset

62 PC87311A SERIAL PORTS

621 Serial Port Registers

Two identical register sets one for each channel are in the

PC87311A All register descriptions in this section apply to

the register sets in both channels

TABLE 6-1 PC87311A UART

DLAB

Selected Register

Receiver Buffer (Read)

Transmitter Holding (Write)

Interrupt Enable

Interrupt Identification (Read)

Line Control

MODEM Control

Line Status

MODEM Status

Scratch (Note 1)

Divisor Latch

(Least Significant Byte)

Divisor Latch

(Most Significant Byte)

Note

This register is only present when operating in the AT NS16450 mode

(XTSEL is low during reset)

622 Line Control Register (LCR)

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit

This is a read and write register Table 6-2 shows the con-

tents of the LCR Details on each bit follow

TLF11362 – 13

FIGURE 6-1 PC87311A Composite Serial Data

Bits 01

These two bits specify the number of data bits in

each transmitted or received serial character The

encoding of bits 0 and 1 is as follows

Bit 1

Bit 0

Data Length

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2

This bit specifies the number of Stop bits transmit-

ted with each serial character If bit 2 is a logic 0

one Stop bit is generated in the transmitted data

If bit 2 is a logic 1 when a 5-bit data length is

selected one and a half Stop bits are generated

If bit 2 is a logic 1 when either a 6- 7- or 8-bit

word length is selected two Stop bits are generat-

ed The receiver checks the first Stop bit only re-

gardless of the number of Stop bits selected

Bit 3

This bit is the Parity Enable bit When bit 3 is a

logic 1 a Parity bit is generated (transmit data) or

checked (receive data) between the last data bit

and Stop bit of the serial data (The Parity bit is

used to produce an even or odd number of 1s

when the data bits and the Parity bit are summed)

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