PC87311AVF datasheet(52/78 Pages) NSC

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60 Serial Ports (Continued)

Bit 7

This bit is permanently set to logic 0

Note

The Line Status Register is intended for read operations

only Writing to this register is not recommended as this

operation is only used for factory testing

625 Interrupt Identification Register (IIR)

In order to provide minimum software overhead during data

character transfers the UART prioritizes interrupts into four

levels and records these in the Interrupt Identification Reg-

ister The four levels of interrupt conditions in order of priori-

ty are Receiver Line Status Received Data Ready Trans-

mitter Holding Register Empty and MODEM Status

When the CPU accesses the IIR the UART freezes all inter-

rupts and indicates the highest priority pending interrupt to

the CPU While this CPU access is occurring the UART

records new interrupts but does not change its current indi-

cation until the current access is complete Table 6-2 shows

the contents of the IIR Details on each bit follow

Bit 0

This bit can be used in an interrupt environment to

indicate whether an interrupt condition is pending

When bit 0 is a logic 0 an interrupt is pending and

the IIR contents may be used as a pointer to the

appropriate interrupt service routine When bit 0 is

a logic 1 no interrupt is pending

Bits 1 2

These two bits of the IIR are used to identify the

highest priority interrupt pending as indicated in

Table 6-5

Bits 3 – 7

These five bits of the IIR are always logic

626 Interrupt Enable Register (IER)

This register enables the four types of UART interrupts

Each interrupt can individually activate the appropriate inter-

rupt (IRQ3 or IRQ4) output signal It is possible to totally

disable the interrupt system by resetting bits 0 through 3 of

the Interrupt Enable Register (IER) Similarly setting bits of

this register to a logic 1 enables the selected interrupt(s)

Disabling an interrupt prevents it from being indicated as

active in the IIR and from activating the interrupt output sig-

nal All other system functions operate in their normal man-

ner including the setting of the Line Status and MODEM

Status Registers Table 6-2 shows the contents of the IER

Details on each bit follow See MODEM Control Register bit

3 for more information on enabling the interrupt pin

Bit 0

This bit enables the Received Data Available Inter-

rupt when set to logic 1

Bit 1

This bit enables the Transmitter Holding Register

Empty Interrupt when set to logic 1

Bit 2

This bit enables the Receiver Line Status Interrupt

when set to logic 1

Bit 3

This bit enables the MODEM Status Interrupt

when set to logic 1

Bits 4 – 7

These four bits are always logic 0

627 Modem Control Register (MCR)

This register controls the interface with the MODEM or data

set (or a peripheral device emulating a MODEM) The con-

tents of the MODEM Control Register (MCR) are indicated

in Table 6-2 and are described below

Bit 0

This bit controls the Data Terminal Ready (DTR)

output When bit 0 is set to a logic 1 the DTR

output is forced to a logic 0 When bit 0 is reset to

a logic 0 the DTR output is forced to a logic 1 In

Local Loopback Mode this bit controls bit 5 of the

MODEM Status Register

Note

The DTR and RTS output of the UART may be applied to

an EIA inverting line driver (such as the DS1488) to ob-

tain the proper polarity input at the MODEM or data set

Bit 1

This bit controls the Request to Send (RTS) out-

put Bit 1 affects the RTS output in a manner iden-

tical to that described above for bit 0 In Local

Loopback Mode this bit controls bit 4 of the

MODEM Status Register

Bit 2

This bit is the OUT1 bit It does not have an output

pin associated with it It can be written to and read

by the CPU In Local Loopback Mode this bit con-

trols bit 6 of the MODEM Status Register

TABLE 6-5 PC87311A Interrupt Control Functions

Interrupt Identification

Interrupt Set and Reset Functions

Bit 2

Bit 1

Bit 0

Priority

Interrupt Type

Interrupt Source

Interrupt Reset Control

Level

None

Highest

Receiver Line Status

Overrun Error Parity Error

Reading the Line

Framing Error or Break

Status Register

Interrupt

Second

Received Data Available

Receiver Data Available

Read Receiver Buffer

Third

Transmitter Holding

Reading the IIR Register

(if Source of Interrupt) or

Writing the Transmitter

Holding Register

Fourth

MODEM Status

Clear to Send or Data Set

Reading the MODEM

Ready or Ring Indicator

Status Register

or Data Carrier Detect

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