PC87311AVF datasheet(16/78 Pages) NSC

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20 Configuration Registers (Continued)

252 Function Address Register (FAR Index e 1)

This register selects the ISA IO address range to which

each peripheral function will respond

Bits 01

These bits select the parallel port address as

shown in Table 2-5

TABLE 2-5 Parallel Port Addresses

Bit

Address

Parallel

Port

Interrupt

LPT2 (378 – 37F)

IRQ5 (Note)

IRQ7

LPT1 (3BC – 3BE)

IRQ7

LPT3 (278 – 27F)

IRQ5

IRQ7

Reserved

TRI-STATE

(CTR4 e 0)

Note

The interrupt assigned to this address can be changed to IRQ7 by

setting Bit 3 of the power and test register

Bits 2–5

These bits determine which ISA IO address range

is associated with each UART (see Tables 2-6a

2-6b)

TABLE 2-6a COM Port Selection for UART1

FAR

UART1

Bit 3

Bit 2

COM

1 (3F8-F)

2 (2F8-F)

3 (Table 2 – 7)

4 (Table 2 – 7)

TABLE 2-6b COM Port Selection for UART2

FAR

UART2

Bit 5

Bit 4

COM

Note

COM3 and COM4 addresses are determined by Bits 6 and 7

Bits 67

These bits select the addresses that will be used

for COM3 and COM4 (see Table 2-7)

TABLE 2-7 Address Selection for COM3 and COM4

Bit 7

Bit 6

COM3 IRQ4

COM4 IRQ3

3E8–Fh

2E8–Fh

338–Fh

238–Fh

2E8–Fh

2E0–7h

220–7h

228–Fh

253 Power and Test Register (PTR Index e 2)

This register determines several power down features the

power down method used when the power down pin

(PWDN) is asserted (crystal and clocks vs clocks only)

whether hardware power down is enabled and provides a

bit for software power down of all enabled functions It se-

lects whether IRQ7 or IRQ5 is associated with LPT2 It puts

the enabled UARTs into their test mode Independent of this

via the Mode Command or the Data Rate Select Register

Bit 0

Setting this bit causes all enabled functions to be

powered down If the crystal power down option is

selected (see Bit 1) the crystal will also be powered

down All register data is retained when the crystal or

clocks are stopped

Bit 1

When the Power Down pin or Bit 0 is asserted this bit

determines whether the enabled functions will have

their internal clocks stopped (Bit 1 e 0) or the exter-

nal crystal (Bit 1 e 1) will be stopped Stopping the

crystal is the lowest power consumption state of the

part

However

if the crystal is stopped

a finite

amount of time (E8 ms) will be required for crystal

stabilization once the Power Down pin (PWDN)or

Bit 0 is deasserted If all internal clocks are stopped

but the crystal continues to oscillate no stabilization

period is required after the Power Down pin or Bit 0 is

deasserted

Bit 2

Setting this bit enables the chip select function of the

PWDN CSOUT pin Resetting this bit enables the

power down function of this pin

Bit 3

Setting this bit associates the parallel port with IRQ7

when the address for the parallel port is 378 – 37Fh

(LPT2) This bit is a ‘‘don’t care’’ when the parallel

port address is 3BC – 3BEh (LPT1) or 278 – 27Fh

(LPT3)

Bit 4

Setting this bit puts UART1 into a test mode which

causes its Baudout clock to be present on its SOUT1

pin if the Line Control Register bit 7 is set to 1

Bit 5

Setting this bit puts UART2 into a test mode which

causes its Baudout clock to be present on its SOUT2

pin if the Line Control Register bit 7 is set to 1

Bit 6

Setting this bit to a one prevents all further write ac-

cesses to the Configuration Registers Once this bit is

set by software it can only be cleared by a hardware

reset After the initial hardware reset this bit is zero

Bit 7

This bit determines the operating mode of the parallel

port If PTR7 is low then the parallel port is in Com-

patible Mode If PTR7 is high then the parallel port is

in Extended Mode This bit will be the inverse of the

state of the POE pin immediately after reset has oc-

curred PTR7 can be programmed at any time

26 POWER DOWN OPTIONS

There are various methods for entering the power down

mode All methods result in one of three possible modes

This section associates the methods of entering the power

down with the resulting mode

Mode 1

The internal clock stops for a specific function (ie

UART1 andor UART2 andor FDC)

This mode is entered by

A Clearing the FER bit for the specific function that will be

powered down See Section 251 FER bits 1 – 3

B Also during reset by setting certain CFG0 – 4 pins See

Table 2-1

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