PC87311AVF datasheet(14/78 Pages) NSC

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20 Configuration Registers (Continued)

TABLE 2-1 Default Configurations Controlled by Hardware

(Continued)

Configuration Pins (CFGn)

(Hex)

Data

Activated Functions

43210

11010

FAR e 11

SEC COM1 COM2 LPT1

11011

FAR e 39

PRI COM3 COM4 LPT1

11100

FAR e 24

PRI COM2 COM3 LPT2

11101

FAR e 38

SEC COM3 COM4 LPT2

11110

FER e 08

FDC

PTR e 00

Power Down Clocks Option

FAR e 10 80

PRI

11111

FER e 00

None

PTR e 02 82

Power Down XTAL and Clocks

FAR e 10

Table 2-1 is organized in the following way The logic values

of the 5 external Configuration Pins are associated with the

resulting Configuration Register Data and the activated

functions The activated functions are grouped into 7 cate-

gories based on the data in the FER In some cases the

data in the FER is given as one of two options This is be-

cause the primary or secondary IDE address is chosen via

the FER

The PTR has one value associated with the active functions

in the FER This value allows the power down of all clocks

when the PWDN pin goes active In the last case where no

functions are active after reset activating the PWDN pin will

also stop the crystal

Most of the variability available is through the FAR Ad-

dresses controlled by the FAR are coded in the following

way

PRI

is the PRImary floppy or IDE address (ie 3F0 – 7h

or 1F0 – 7 3F6 7h)

SEC

is the SECondary IDE address (170 – 7 376 7h)

COM1 is the UART address at 3F8 – Fh

COM2 is the UART address at 2F8 – Fh

COM3 is the UART address at 3E8 – Fh

COM4 is the UART address at 2E8 – Fh

LPT1

is the parallel port (

ll PORT ) address at 3BC–3BEh

LPT2

is the

ll PORT address at 378–37Fh

The chosen addresses are given under active functions and

are in the same order as the active functions they are asso-

ciated with In other words if the active functions are given

as FDC IDE UART1 UART2

ll PORT and the addresses

are given as PRI PRI COM1 COM2 LPT2 then the func-

tions and the addresses are associated as follows FDC e

PRI IDE e PRI UART1 e COM1 UART2 e COM2

ll PORT e LPT2

24 INDEX AND DATA REGISTERS

One more general aspect of the Configuration Registers is

that the Index and the Data Register pair can be relocated

to any one of two locations This is controlled through a

hardware strapping option on one pin (BADDR0) and it al-

lows the registers to avoid conflicts with other adapters in

the IO address space Table 2-2 shows the address op-

tions

TABLE 2-2 Index and Data

BADDR0

Index Addr

Data Addr

398h

399h

26Eh

26Fh

25 BASE CONFIGURATION REGISTERS

251 Function Enable Register (FER Index 0)

This register enables and disables all major chip functions

Disabled functions have their clocks automatically powered

down but the data in their registers remains intact It also

selects whether the FDC and the IDE controller will be lo-

cated at their primary or secondary address

Bit 0

When this bit is one the parallel port can be accessed

at the address specified in the FAR

Bit 1

When this bit is one UART1 can be accessed at the

address specified in the FAR When this bit is zero

access to UART1 is blocked and it will be in power

down mode The UART1 registers retain all data in

power down mode Caution Any UART1 interrupt

that is enabled and active or becomes active after

UART1 is disabled will assert the associated IRQ pin

when UART1 is disabled If disabling UART1 via soft-

ware clear the IRQ Enable bit (MCR3) to zero before

clearing FER 1 This is not an issue after reset be-

cause MCR3 will be zero until it is written

Bit 2

When this bit is one UART2 can be accessed at the

address specified in the FAR When this bit is zero

access to UART2 is blocked and it will be in power

down mode The UART2 registers retain all data in

power down mode Caution Any UART2 interrupt

that is enabled and active or becomes active after

UART2 is disabled will assert the associated IRQ pin

when UART2 is disabled If disabling UART2 via soft-

ware clear the IRQ Enable bit (MCR3) to zero before

clearing FER2 This is not an issue after reset be-

cause MCR3 will be zero until it is written

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