PC97307 datasheet(118/218 Pages) NSC

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Parallel Port (Logical Device 4)

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EPP 1.7 Data Write and Read

This procedure writes to the selected peripheral device or

EPP 1.7 data read or write operations are similar to EPP 1.7

Address register read or write operations, except that the

data strobe (DSTRB signal), and the EPP Data register, re-

place the address strobe (ASTRB signal) and the EPP Ad-

dress register, respectively.

EPP Revision 1.7 and 1.9 Zero Wait State (ZWS)

Address Write and Read Operations

The following procedure performs a short write to the select-

ed peripheral device or register. See also Figure 6-14.

1. The system writes a byte to the EPP Address register.

WR becomes low to latch D7-0 into the EPP Data regis-

ter. The latch drives the EPP Data register to PD7-0.

2. The EPP first pulls WRITE low, and then pulls ASTRB

low to indicate that data has been sent.

3. If WAIT was high during the system write cycle, ZWS

goes low and IOCHRDY stays high.

4. When the system pulls WR high, the EPP pulls ASTRB,

ZWS and then WRITE to high. The EPP can change

PD7-0 only when WRITE and ASTRB are high.

5. If the peripheral is fast enough to pull WAIT low before

the system terminates the write cycle, the EPP pulls

IOCHRDY to low, but does not pull ZWS to low, thus

carrying out a normal (non-ZWS EPP 1.7) write opera-

tion.

FIGURE 6-14. EPP Write with Zero Wait States

A read operation is similar, except for the data direction, ac-

tivation of RD instead of WR, and WRITE stays high.

6.3.11

EPP 1.7 and 1.9 Zero Wait State Data Write and

Read Operations

EPP 1.7 zero wait state data write and read operations are

similar to EPP zero wait state address write and read oper-

ations, with the exception that the data strobe (DSTRB sig-

nal), and a data register, replace the address strobe

(ASTRB signal) and the address register, respectively.

D7-0

WAIT

DSTRB or

WRITE

PD7-0

IOCHRDY

ZWS

ASTRB

EPP 1.9 Address Write

The following procedure selects a peripheral or register as

shown in Figure 6-15.

1. The system writes a byte to the EPP Address register.

2. The EPP pulls IOCHRDY low, and waits for WAIT to be-

come low.

3. When WAIT becomes low, the EPP pulls WRITE to low

and drives the latched byte onto PD7-0. If WAIT was al-

ready low, steps 2 and 3 occur concurrently.

4. The EPP pulls ASTRB low and waits for WAIT to be-

come high.

5. When WAIT becomes high, the EPP stops pulling

IOCHRDY low, and waits for WR to become high.

6. When WR becomes high, the EPP pulls ASTRB high,

and waits for WAIT to become low.

7. If no EPP write is pending when WAIT becomes low, the

EPP pulls WRITE to high. Otherwise, WRITE remains

low, and the EPP may change PD7-0.

FIGURE 6-15. EPP 1.9 Address Write

EPP 1.9 Address Read

The following procedure reads from the address register.

1. The system reads a byte from the EPP address register.

When RD becomes low, the EPP pulls IOCHRDY low,

and waits for WAIT to become low.

2. When WAIT becomes low, the EPP pulls ASTRB low

and waits for WAIT to become high. If WAIT was already

low, steps 2 and 3 occur concurrently.

3. When WAIT becomes high, the EPP stops pulling IO-

CHRDY low, and waits for RD to become high.

4. When RD becomes high, the EPP latches PD7-0 (to

provide sufficient hold time), pulls ASTRB high, and puts

D7-0 in TRI-STATE.

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

ZWS

PC97307 Datasheet(PDF) 118 Page - National Semiconductor (TI)

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