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PC97307 Datasheet(PDF) 121 Page - National Semiconductor (TI) |
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PC97307 Datasheet(HTML) 121 Page - National Semiconductor (TI) |
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121 / 218 page ![]() 121 Parallel Port (Logical Device 4) www.national.com 6.5.3 ECP Data Register (DATAR), Bits 7-5 of ECR = 000 or 001, Offset 000h The ECP Data Register (DATAR) register is the same as the DTR register (see Section 6.2.2), except that a read al- ways returns the values of the PD7-0 signals instead of the register latched data. FIGURE 6-17. DATAR Register Bitmap 6.5.4 ECP Address FIFO (AFIFO) Register, Bits 7-5 of ECR = 011, Offset 000h The ECP Address FIFO Register (AFIFO) is write only. In the forward direction (when bit 5 of DCR is 0) a byte written into this register is pushed into the FIFO and tagged as a command. Reading this register returns undefined contents. Writing to this register in a backward direction (when bit 5 of DCR is 1) has no effect and the data is ignored. FIGURE 6-18. AFIFO Register Bitmap 76543210 Reset Required 0 0 0 0 0 0 0 0 ECP Data Register (DATAR) Offset 000h D2 D4 D5 D6 D7 D0 D1 D3 Bits 7-5 of ECR = 000 or 001 Data Bits 76543210 Reset Required 0 0 0 0 0 0 0 0 ECP Address Register (AFIFO) Offset 000h A2 A4 A5 A6 A7 A0 A1 A3 Bits 7-5 of ECR = 011 Address Bits 6.5.5 ECP Status Register (DSR), Offset 001h This read-only register displays device status. Writes to this DSR have no effect and the data is ignored. This register should not be confused with the DSR register of the Floppy Disk Controller (FDC). FIGURE 6-19. ECP DSR Register Bitmap Bits 0 - EPP Time-Out Status In EPP modes only, this is the time-out status bit. In all other modes this bit has no function and has the con- stant value 1. This bit is cleared when an EPP mode is enabled. Thereafter, this bit is set to 1 when a time-out occurs in an EPP cycle and is cleared when DSR is read. In EPP modes: 0 - An EPP mode is set. No time-out occurred since DSR was last read. 1 - Time-out occurred on EPP cycle (minimum of 10 µsec). (Default) Bits 2,1 - Reserved These bits are reserved and are always 1. Bit 3 - ERR Status This bit reflects the status of the ERR signal. 0 - Printer error. 1 - No printer error. Bit 4 - SLCT Status This bit reflects the status of the Select signal. The print- er sets this signal high when it is online and selected 0 - Printer not selected. (Default) 1 - Printer selected and on-line. Bit 5 - PE Status This bit reflects the status of the Paper End (PE) signal. 0 - Paper not ended. 1 - No paper in printer. Bit 6 - ACK Status This bit reflects the status of the ACK signal. This signal is pulsed low after a character is received. 0 - Character received. 1 - No character received. (Default) 76543210 Reset Required 1 1 1 1 1 ECP Status Register (DSR) Offset 001h Reserved SLCT Status PE Status ACK Status Printer Status EPP Time-Out Status Reserved ERR Status |
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