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PC97307 Datasheet(PDF) 193 Page - National Semiconductor (TI) |
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PC97307 Datasheet(HTML) 193 Page - National Semiconductor (TI) |
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193 / 218 page ![]() 193 Device Description www.national.com 13.3.3 Microprocessor Interface Timing TABLE 13-37. Microprocessor Interface Timing a. Not tested. Guaranteed by design. Symbol Parameter Min Max Unit tAR Valid Address to Read Active 18 nsec tAW Valid Address to Write Active 18 nsec tDH Data Hold 0 nsec tDS Data Setup 18 nsec tHZ Read to Floating Data Bus a 13 25 nsec tPS Port Setup 10 nsec tRA Address Hold from Inactive Read 0 nsec tRCU Read Cycle Update a 45 nsec tRD Read Strobe Width 60 nsec tRDH Read Data Hold 10 nsec tRI Read Strobe to Clear FDC IRQ 55 nsec tRVD Active Read to Valid Data 55 nsec tWA Address Hold from Inactive Write 0 nsec tWCU Write Cycle Update a 45 nsec tWI Write Strobe to Clear FDC IRQ 55 nsec tWO Write Data to Port Update 60 nsec tWR Write Strobe Width 60 nsec RC Read Cycle = tAR + tRD + tRCU a 123 nsec WC Write Cycle = tAW + tWR + tWC a 123 nsec tWRR RD low after WR high a 80 nsec |
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