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PC97307 Datasheet(PDF) 195 Page - National Semiconductor (TI) |
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PC97307 Datasheet(HTML) 195 Page - National Semiconductor (TI) |
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195 / 218 page  195 Device Description www.national.com FIGURE 13-5. Read After Write Operation to All Registers and RAM 13.3.4 Baud Output Timing TABLE 13-38. Baud Output Timing FIGURE 13-6. Baud Output Timing a. Not tested. Guaranteed by design. Symbol Parameter Conditions Min Max Unit N Baud Divisor 1 65535 nsec tBHD Baud Output Positive Edge Delay a CLK = 24 MHz/2, 100 pF load 56 nsec tBLD Baud Output Negative Edge Delay a CLK = 24 MHz/2, 100 pF load 56 nsec A15-0 D7-0 AEN WR (Input) tWRR or CS RD CLK BAUD OUT (÷1) BAUD OUT ( ÷2) BAUD OUT ( ÷3) BAUD OUT ( ÷N, N > 3) tBLD tBLD tBLD tBLD tBLD tBHD tBHD tBHD N |
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