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PC97307 Datasheet(PDF) 198 Page - National Semiconductor (TI) |
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PC97307 Datasheet(HTML) 198 Page - National Semiconductor (TI) |
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198 / 218 page  198 Device Description www.national.com Note: If SCR0 = 1, then tSINT = 3 RCLKs. For a time-out interrupt, tSINT = 8 RCLKs. FIGURE 13-9. FIFO Mode Receiver Timing Note: If SCR0 = 1, then tSINT = 3 RCLKs. For a time-out interrupt, tSINT = 8 RCLKs FIGURE 13-10. Time-Out Receiver Timing SIN Sample Clock Trigger Interrupt tRAI2 Data (5-8) Stop Active Active LSI Interrupt RD (RD LSR) RD (RD RBR) (FIFO at or above Trigger Level) (FIFO Below Trigger Level) Level tRINT tSINT Note tRAI3 Active tRINT tSINT Active Active Top Byte of FIFO Stop Note tSINT Previous Byte Read From FIFO SIN Sample Clock Time-Out or Interrupt LSI Interrupt RD (RD LSR) RD (RD RBR) (FIFO at or above Trigger Level) (FIFO Below Trigger Level) Trigger Level |
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