PC87317 datasheet(6/272 Pages) NSC

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Table of Contents

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2.10.6

CS1 Base Address LSB Register ................................................................................ 43

2.10.7

CS1 Configuration Register ......................................................................................... 43

2.10.8

Reserved ..................................................................................................................... 44

2.10.9

CS2 Base Address MSB Register ............................................................................... 44

2.10.10 CS2 Base Address LSB Register ................................................................................ 44

2.10.11 CS2 Configuration Register ......................................................................................... 44

2.10.12 Reserved, Second Level Indexes 0Bh-0Fh ................................................................. 44

2.10.13 Not Accessible, Second Level Indexes 10h-FFh ......................................................... 44

2.11

CONFIGURATION REGISTER BITMAPS ................................................................................ 44

3.0

Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1)

3.1

SYSTEM ARCHITECTURE ....................................................................................................... 47

3.2

FUNCTIONAL OVERVIEW ....................................................................................................... 48

3.3

DEVICE CONFIGURATION ...................................................................................................... 48

3.3.1

I/O Address Space ...................................................................................................... 48

3.3.2

Interrupt Request Signals ............................................................................................ 48

3.3.3

KBC Clock ................................................................................................................... 49

3.3.4

Timer or Event Counter ............................................................................................... 50

3.4

EXTERNAL I/O INTERFACES .................................................................................................. 50

3.4.1

Keyboard and Mouse Interface ................................................................................... 50

3.4.2

General Purpose I/O Signals ....................................................................................... 50

3.5

INTERNAL KBC - PC87317VUL INTERFACE .......................................................................... 51

3.5.1

The KBC DBBOUT Register, Offset 60h, Read Only .................................................. 52

3.5.2

The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............ 52

3.5.3

The KBC STATUS Register ........................................................................................ 52

3.6

INSTRUCTION TIMING ............................................................................................................. 52

4.0

Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)

4.1

RTC OVERVIEW ....................................................................................................................... 53

4.1.1

RTC Hardware and Functional Description ................................................................. 53

4.1.2

Timekeeping ................................................................................................................ 54

4.1.3

Power Management .................................................................................................... 55

4.1.4

Interrupt Handling ........................................................................................................ 56

4.2

THE RTC REGISTERS ............................................................................................................. 56

4.2.1

RTC Control Register A (CRA) .................................................................................... 56

4.2.2

RTC Control Register B (CRB) .................................................................................... 57

4.2.3

RTC Control Register C (CRC) ................................................................................... 58

4.2.4

RTC Control Register D (CRD) ................................................................................... 58

4.2.5

Date-of-Month Alarm Register (DMAR ........................................................................ 59

4.2.6

Month Alarm Register (MAR) ...................................................................................... 59

4.2.7

Century Register (CR) ................................................................................................. 59

4.3

APC OVERVIEW ....................................................................................................................... 59

4.3.1

System Power States .................................................................................................. 61

4.3.2

System Power Switching Logic ................................................................................... 62

4.4

APC DETAILED DESCRIPTION ............................................................................................... 62

PC87317 Datasheet(PDF) 6 Page - National Semiconductor (TI)

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