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PC87317 Datasheet(PDF) 77 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC87317
Description  PC87317VUL/PC97317VUL SuperI/O Plug and Play Compatible with ACPI Compliant Controller/Extender
PDF  272 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87317 Datasheet(HTML) 77 Page - National Semiconductor (TI)

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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
77
www.national.com
4.5.15
APC Status Register 1 (APSR1)
This is read-only register. The bit settings are unaffected by
Master Reset.
FIGURE 4-28. APSR1 Register Bitmap
Bit 0 - Switch Pin Status
This bit is holds the value of the SWITCH pin (before the
debouncer).
Bit 1 - Switch On event Detect
This bit is set to 1 when a Switch On event is detected,
regardless of the Power Button Enable bit (See “Bit 0 -
Power Button Enable (PWRBTN_EN)” on page 79). It is
cleared to 0 when the register is read.
Bits 7-2 - Reserved
4.5.16
Day-of-Month Alarm Address Register
(DADDR)
This register defines the Day-of-Month Alarm register loca-
tion. The bit settings are unaffected by Master Reset.
FIGURE 4-29. DADDR Register Bitmap
Bits 6-0 - Offset Address of the Day-of-Month Alarm
Register
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to C9h.
4.5.17
Month Alarm Address Register (MADDR)
This register defines the Month Alarm register location. The
bit settings are unaffected by Master Reset.
FIGURE 4-30. MADDR Register Bitmap
Bits 6-0 - Offset Address of the Month Alarm Register
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to CAh.
4.5.18
Century Address Register (CADDR)
This register defines the Century register location. The bit
settings are unaffected by Master Reset.
FIGURE 4-31. CADDR Register Bitmap
Bits 6-0 - Offset Address of the Century Register
Bit 0 is the least significant bit of the address.
Bit 7 - Bank Select
0: Bank 0.
1: Bank 1.
Upon first power on, it is initialized to C8h.
Reserved
76543210
SWITCH pin status
Switch-On Event detect
Bank 2,
Power-Up
Required
APC Status
(APSR1)
Reset
Register 1
X
0
Index 4Eh
Bank Select
76543210
1
0
0
1
0
0
1
1
Bank 2
Power-Up
Required
Day-of-Month Alarm Address
(DADDR)
Reset
Register
Day-of-Month
Alarm Address
Index 4Fh
Bank Select
76543210
0
1
0
1
0
0
1
1
Bank 2
Power-Up
Required
Month Alarm Address
(MADDR)
Reset
Register
Month
Alarm Address
Index 50h
Bank Select
76543210
0
0
0
1
0
0
1
1
Bank 2
Power-Up
Required
Century Address
(CADDR)
Reset
Register
Century Address
Index 51h



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