PC87317 datasheet(18/272 Pages) NSC

18 / 272 page

Signal/Pin Connection and Description

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CFG1-0

144, 138

Conﬁguration

Input

Group 5

Configuration Strap Pins 1-0 – These pins determine the default

configuration upon power up. These pins are pulled down by internal

30 K

Ω resistors. Use external 10 KΩ pull-up resistors to V

DD.

CFG1 is multiplexed with DTR2 and BOUT2. CFG0 is multiplexed with

SOUT1. See Table 2-2 on page 28.

CS0

106

General

Purpose

Output

Group 21

Group 12

Programmable Chip Select – CS0, CS1 and CS2 are programmable

chip select and/or latch enable and/or output enable signals that have

many uses, for example, as game ports or for I/O port expansion.

The decoded address and the assertion conditions are conﬁgured via

the chip conﬁguration registers. See Section 2.3 on page 29.

CS0 is multiplexed with LED on pin 68 and with P12 on pin 106. On

pin 68 is an open-drain output that is in TRI-STATE unless VDD is

applied.

CS1 is multiplexed with CSOUT-NSC-Test/XD0.

CS2 is multiplexed with XD1.

CS2,1

72, 71

General

Purpose

I/O

Group 9

CSOUT-

NSC-Test

NSC-use

Output

Group 21

Chip Select Read Output, NSC-Test – National Semiconductor test

output. This is an open-drain output signal.

This signal is multiplexed with CS1 and XD0.

CTS2,1

141, 131

UART1,

UART2

Input

Group 1

UART1 and UART2 Clear to Send – When low, these signals indicate

that the modem or other data transfer device is ready to exchange data.

CTS2 is multiplexed with GPIO30.

D7-0

10-3

ISA-Bus

I/O

Group 8

ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is

the LSB and D7 is the MSB. These signals have 24 mA (sink)

buffered outputs.

DACK3-0

59-56

ISA-Bus

Input

Group 1

DMA Acknowledge 0,1,2 and 3 – These active low input signals

acknowledge a request for DMA services and enable the IOWR and

IORD input signals during a DMA transfer. These DMA signals can be

mapped to the following logical devices: FDC, UART1, UART2 or

parallel port.

DCD2,1

142, 132

UART1,

UART2

Input

Group 1

UART1 and UART2 Data Carrier Detected – When low, this signal

indicates that the modem or other data transfer device has detected

the data carrier.

DCD2 is multiplexed with GPIO31

DENSEL

FDC

Output

Group 16

Density Select – Indicates that a high FDC density data rate (500

Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is

selected.

DENSELs polarity is controlled by bit 5 of the SuperI/O FDC

Conﬁguration register as described in Section 2.6.1 on page 40.

DIR

FDC

Output

Group 16

Direction – This output signal determines the direction of the Floppy

Disk Drive (FDD) head movement (active = step in, inactive = step

out) during a seek operation. During reads or writes, DIR is inactive.

DR1,0

88, 87

FDC

Output

Group 16

Drive Select 0 and 1 – These active low output signals are the

decoded drive select output signals. DR0 and DR1 are controlled by

Digital Output Register (DOR) bits 0 and 1. They are encoded with

information to control four FDDs when bit 7 of the SuperI/O FDC

Conﬁguration register is 1, as described in Section 2.6.1.

See MTR0,1 for more information.

DRATE0

FDC

Output

Group 20

Data Rate 0 – This output signal reflects the value of bit 0 of the

Conﬁguration Control Register (CCR) or the Data Rate Select Register

(DSR), whichever was written to last. Output from the pin is totem-pole

buffered (6 mA sink, 6 mA source).

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

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