PC87317 datasheet(8/272 Pages) NSC

8 / 272 page

Table of Contents

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4.8.2

APC Register Bitmaps ................................................................................................. 84

4.9

REGISTER BANK TABLES ....................................................................................................... 89

5.0

The Digital Floppy Disk Controller (FDC) (Logical Device 3)

5.1

FDC FUNCTIONS ..................................................................................................................... 92

5.1.1

Microprocessor Interface ............................................................................................. 92

5.1.2

System Operation Modes ............................................................................................ 92

5.2

DATA TRANSFER ..................................................................................................................... 93

5.2.1

Data Rates ................................................................................................................... 93

5.2.2

The Data Separator ..................................................................................................... 93

5.2.3

Perpendicular Recording Mode Support ..................................................................... 94

5.2.4

Data Rate Selection ..................................................................................................... 94

5.2.5

Write Precompensation ............................................................................................... 95

5.2.6

FDC Low-Power Mode Logic ....................................................................................... 95

5.2.7

Reset ........................................................................................................................... 95

5.3

THE FDC REGISTERS ............................................................................................................. 96

5.3.1

Status Register A (SRA) .............................................................................................. 96

5.3.2

Status Register B (SRB) .............................................................................................. 97

5.3.3

Digital Output Register (DOR) ..................................................................................... 97

5.3.4

Tape Drive Register (TDR) .......................................................................................... 99

5.3.5

Main Status Register (MSR) ...................................................................................... 100

5.3.6

Data Rate Select Register (DSR) .............................................................................. 101

5.3.7

Data Register (FIFO) ................................................................................................. 102

5.3.8

Digital Input Register (DIR) ........................................................................................ 103

5.3.9

Configuration Control Register (CCR) ....................................................................... 104

5.4

THE PHASES OF FDC COMMANDS ..................................................................................... 104

5.4.1

Command Phase ....................................................................................................... 104

5.4.2

Execution Phase ........................................................................................................ 104

5.4.3

Result Phase ............................................................................................................. 106

5.4.4

Idle Phase .................................................................................................................. 106

5.4.5

Drive Polling Phase ................................................................................................... 106

5.5

THE RESULT PHASE STATUS REGISTERS ........................................................................ 107

5.5.1

Result Phase Status Register 0 (ST0) ....................................................................... 107

5.5.2

Result Phase Status Register 1 (ST1) ....................................................................... 107

5.5.3

Result Phase Status Register 2 (ST2) ....................................................................... 108

5.5.4

Result Phase Status Register 3 (ST3) ....................................................................... 109

5.6

FDC REGISTER BITMAPS ..................................................................................................... 109

5.6.1

Standard .................................................................................................................... 109

5.6.2

Result Phase Status .................................................................................................. 111

5.7

THE FDC COMMAND SET ..................................................................................................... 112

5.7.1

Abbreviations Used in FDC Commands .................................................................... 113

5.7.2

The CONFIGURE Command .................................................................................... 114

5.7.3

The DUMPREG Command ....................................................................................... 114

5.7.4

The FORMAT TRACK Command ............................................................................. 115

5.7.5

The INVALID Command ............................................................................................ 117

5.7.6

The LOCK Command ................................................................................................ 118

PC87317 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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