PC87332 datasheet(24/98 Pages) NSC

24 / 98 page

20 Configuration Registers (Continued)

Bit 5

Zero Wait State enable bit If this bit is 1 (and pin 31

(PQFPTQFP) is configured as ZWS) ZWS is driven

low when the Enhanced Parallel Port (EPP) or the

ECP can accept a short host readwrite-cycle other-

wise the ZWS open drain output is not driven EPP

ZWS operation should be configured when the sys-

tem is fast enough to support it

Bit 6

ZWS PWDN select bit When this bit is 0 the ZWS

pin is Zero Wait State output

When this bit is 1 the PWDN CSOUT pin option is

selected

Bit 7

IOCHRDYMFM select bit When this bit is 0 the

IOCHRDY pin is the IOCHRDY open drain output that

extends the host-EPP cycle when required

When this bit is 1 the MFM pin is selected

255 Printer Control Register (PCR Index e 04h)

This register enables the EPP ECP version modes and

interrupt options On reset all the PCR bits are cleared to 0

The parallel port mode is software configurable as follows

TABLE 2-10 Parallel Port Mode

Operation

FER

PTR

PCR

Mode

Bit 0

Bit 7

Bit 0

Bit 2

None

Compatible

1000

Extended

1100

EPP

ECP

Bit 0

EPP enable bit When this bit is 0 the EPP is disabled

and the EPP registers are not accessible (access ig-

nored)

When this bit is 1 and bit 2 of PCR is 0 the EPP is

enabled Note that the EPP should not be configured

with base address 3BCh

Bit 1

EPP version select bit When this bit is 0 Version 17 is

supported

When this bit is 1 Version 19 is supported (IEEE

1284)

Bit 2

ECP enable bit When this bit is 0 the ECP is disabled

and in power mode The ECP registers are not acces-

sible (access ignored) the ECP interrupt is inactive

and the DMA request pin is in TRI-STATE The IRQ57

inputs are blocked to reduce their leakage currents

When this bit is 1 the ECP is enabled The software

should change this bit to 1 only when bits 0 1 and 2 of

the existing CTR are 1 0 and 0 respectively

Bit 3

ECP Clock Freeze Control Bit In power-down modes

2 and 3 When this bit is 0 the clock provided to the

ECP is stopped and

When this bit is 1 the clock provided to the ECP is not

stopped

Note

When either this bit or the ECP enable bit is 0 there is no

change in the PC87334 crystal stopping mechanism

Bit 4

Reserved This bit must be set to 0

Bit 5

Parallel port interrupt (IRQ5 or IRQ7) polarity control

bit

When this bit is 0 the interrupt polarity is as already

defined and the ECP interrupt is level high or nega-

tive pulse

When this bit is 1 the interrupt polarity is inverted

Bit 6

Parallel port interrupt (IRQ5 or IRQ7) open drain con-

trol bit

When this bit is 0 the configured interrupt line (IRQ5

or IRQ7) has a totem-pole TRI-STATE output

When this bit is 1 the configured interrupt line has an

open drain output (drive low or TRI-STATE no drive

high no internal pullup)

Bit 7

Reserved

maintain

compatibility

with

future

SuperIO devices this bit must not be modified when

this register is written Use read-modify-write to pre-

serve the value of this bit

256 Power Management Control Register

(PMC Index e 06h)

This register controls the TRI-STATE and input pins The

PMC Register is accessed through Index 06h The PMC

Bit 0

IDE TRI-STATE control bit When this bit is 1 and ei-

ther the IDE is disabled or the SuperIO is in power-

down mode HCS0 and HCS1 are in TRI-STATE

IDED7 input is also blocked to reduce leakage current

and its value is undefined when IDE is disabled

Bit 1

FDC TRI-STATE control bit When this bit is 1 and the

FDC is powered-down the FDC outputs are in TRI-

STATE (except IRQ6 PD IDLE and the PPM outputs

even if the PPM is used as FDC pins) and the FDC

inputs (except DSKCHG) are blocked to reduce their

leakage current

Bit 2

UARTs TRI-STATE control bit When this bit is 1 and

any UART is powered-down the outputs of that UART

are in TRI-STATE (except IRQ3 and IRQ4) and the

inputs are blocked to reduce their leakage current

The values of the blocked inputs are SINe1 CTSe1

DSRe1 DCDe1 and RIe1

Bit 3

ECP DMA configuration bit When this bit is 0 ECP

DMA is not configura ble IDENTPDACK is assumed

to be 1 and PDRQ is in TRI-STATE

When this bit is 1 ECP DMA is configurable via an

ECP control register Pins 54 and 33 are PDACK and

PDRQ respectively IDENT is assumed to be 1

Note

This bit must not be set when the PC87332 is assembled into a

PC87312PC87322 socket in which pin 33 is VDDA

Bit 4

PD and IDLE (FDC power management output pins)

enable bit

When this bit is 0 pins 43 and 45 are MTR1 and DR1

respectively

When this bit is 1 pins 43 and 45 are IDLE and PD

respectively

Bit 5

Selective Lock bit This bit enables locking of the fol-

lowing configuration bits bit 5 of PMC bit 4 of FER

bits 0 – 7 of FAR bits 2 – 3 of PTR bits 6 – 7 of FCR

and bit 0 of TUP Unlike bit 6 of PTR it does not lock

all the configuration bits

Once this bit is set by software it can only be cleared

by a hardware reset This bit should be used instead of

bit 6 of PTR if a configuration bit should be dynamically

modified by software (like PMC bits)

PC87332 Datasheet(PDF) 24 Page - National Semiconductor (TI)

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