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PC87332 Datasheet(PDF) 33 Page - National Semiconductor (TI) |
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PC87332 Datasheet(HTML) 33 Page - National Semiconductor (TI) |
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33 / 98 page ![]() 30 FDC Register Description (Continued) CCRModel 30 Mode D7 D6 D5 D4 D3 D2 D1 D0 DESC 0 0 0 0 0 NOPRE DRATE1 DRATE0 RESET NA NA NA NA NA NA 1 0 COND D7–3 Reserved Should be set to 0 D2 No Precompensation This bit can be set by soft- ware to indicate no precompensation It can be read by bit D2 of the DIR when in the Model 30 register mode This bit is unaffected by a software reset D1 – 0 Data Rate Select 10 These bits determine the data rate of the floppy controller See Table 3-7 for the appropriate values 32 RESULT PHASE STATUS REGISTERS The Result Phase of a command contains bytes that hold status information The format of these bytes are described below Do not confuse these status bytes with the Main Status Register which is a read only register that is always valid The Result Phase status registers are read from the Data Register (FIFO) only during the Result Phase of certain commands (see Section 41 Command Set Summary) The status of each register bit is indicated when the bit is a 1 321 Status Register 0 (ST0) D7 D6 D5 D4 D3 D2 D1 D0 DESC IC IC SE EC 0 HDS DS1 DS0 RESET 00 0 0 0 0 0 0 COND D7–6 Interrupt Code 00 e Normal Termination of Command 01 e Abnormal Termination of Command Execu- tion of command was started but was not successfully completed 10 e Invalid Command Issued Command issued was not recognized as a valid command 11 e Internal drive ready status changed state dur- ing the drive polling mode Only occurs after a hardware or software reset D5 Seek End Seek Relative Seek or Recalibrate command completed by the controller (Used during a Sense Interrupt command) D4 Equipment Check After a Recalibrate command Track 0 signal failed to occur (Used during Sense Interrupt command) D3 Not Used Always 0 D2 Head Select Indicates the active high status of the HDSEL pin at the end of the Execution Phase D1 – 0 Drive Select 10 These two binary encoded bits indicate the logical drive selected at the end of the Execution Phase 00 e Drive 0 selected 01 e Drive 1 selected 10 e Drive 2 selected 11 e Drive 3 selected 322 Status Register 1 (ST1) D7 D6 D5 D4 D3 D2 D1 D0 DESC ET 0 CE OR 0 ND NW MA RESET 00 0 0 0 0 0 0 COND D7 End of Track Controller transferred the last byte of the last sector without the Terminal Count (TC) pin 64 (PQFPTQFP) becoming active The last sector is the End of Track sector number programmed in the Command Phase D6 Not Used Always 0 D5 CRC Error If this bit is set and bit 5 of ST2 is clear then there was a CRC error in the Address Field of the correct sector If bit 5 of ST2 is also set then there was a CRC error in the Data Field D4 Overrun Controller was not serviced by the mP soon enough during a data transfer in the Execution Phase For read operations indicates a data over- run For write operations indicates a data underrun D3 Not Used Always 0 D2 No Data Three possible problems 1 Controller cannot find the sector specified in the Command Phase during the execution of a Read Write Scan or Verify command An address mark was found however so it is not a blank disk 2 Controller cannot read any Address Fields with- out a CRC error during a Read ID command 3 Controller cannot find starting sector during exe- cution of Read A Track command D1 Not Writable Write Protect pin is active when a Write or Format command is issued D0 Missing Address Mark If bit 0 of ST2 is clear then the controller cannot detect any Address Field Ad- dress Mark after two disk revolutions If bit 0 of ST2 is set then the controller cannot detect the Data Field Address Mark after finding the correct Ad- dress Field 323 Status Register 2 (ST2) D7 D6 D5 D4 D3 D2 D1 D0 DESC 0 CM CD WT SEH SNS BT MD RESET 0 000 0 0 0 0 COND D7 Not Used Always 0 D6 Control Mark Controller tried to read a sector which contained a deleted data address mark dur- ing execution of Read Data or Scan commands Or if a Read Deleted Data command was executed a regular address mark was detected D5 CRC Error in Data Field Controller detected a CRC error in the Data Field Bit 5 of ST1 is also set D4 Wrong Track Only set if desired sector is not found and the track number recorded on any sector of the current track is different from the track ad- dress specified in the Command Phase D3 Scan Equal Hit ‘‘Equal’’ condition satisfied during any Scan command 33 |
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