PC87332 datasheet(19/98 Pages) NSC

19 / 98 page

20 Configuration Registers (Continued)

23 HARDWARE CONFIGURATION

During reset one of 32 possible sets of default values are

loaded into the first three Configuration Registers A strap-

ping option on five pins (CFG0 – 4) selects the set of values

that is loaded This allows for automatic configuration with-

out software intervention Table 2-1 shows the 32 possible

default configurations The default configuration can be

modified by software at any time after reset by using the

access procedure described in the Software Configuration

Section

Table 2-1 is organized as follows The logic values of the

five external Configuration Pins are associated with the re-

sulting Configuration Register Data and the activated func-

tions The activated functions are grouped into seven cate-

gories based on the data in the FER In some cases the

data in the FER is given as one of two options This is be-

cause the primary or secondary IDE address is chosen via

the FER

The PTR has one value associated with the active functions

in the FER This value allows the power-down of all clocks

when the PWDN pin goes active In the last case where no

functions are active after reset activating the PWDN pin

also stops the crystal

Most of the variability available is through the FAR Ad-

dresses controlled by the FAR are coded as follows

PRI

is the PRImary floppy or IDE address (ie 3F0 – 7h

or 1F0 – 7 3F6 7h)

SEC

is the SECondary IDE address (170 – 7 376 7h)

COM1 is the UART address at 3F8 – Fh

COM2 is the UART address at 2F8 – Fh

COM3 is the UART address at 3E8 – Fh

COM4 is the UART address at 2E8 – Fh

LPTA

is the parallel port (

ll PORT ) address at 3BC–

3BEh

LPTB

is the

ll PORT address at 378–37Fh

The chosen addresses are given under active functions and

are in the same order as the active functions with which

they are associated In other words if the active functions

are given as FDC IDE UART1 UART2

ll PORT and the

addresses are given as PRI PRI COM1 COM2 LPTB then

the functions and the addresses are associated as follows

FDC

PRI

IDE

PRI

UART1

COM1

UART2 e COM2

ll PORT e LPTB

TABLE 2-1 Default Configurations Controlled by Hardware

Configuration Pins (CFGn)

(Hex)

Data

Activated Functions

43210

FER e 4F CF

FDC IDE UART1 UART2

ll PORT

PTR e 00 80

Power-Down Clocks Option

00000

FAR e 10

PRI PRI COM1 COM2 LPTB

00001

FAR e 11

PRI PRI COM1 COM2 LPTA

00010

FAR e 11

PRI SEC COM1 COM2 LPTA

00011

FAR e 39

PRI PRI COM3 COM4 LPTA

00100

FAR e 24

PRI PRI COM2 COM3 LPTB

00101

FAR e 38

PRI SEC COM3 COM4 LPTB

FER e 4B CB

FDC IDE UART1

ll PORT

PTR e 00 80

Power-Down Clocks Option

00110

FAR e 00

PRI PRI COM1 LPTB

00111

FAR e 01

PRI PRI COM1 LPTA

01000

FAR e 01

PRI SEC COM1 LPTA

01001

FAR e 09

PRI PRI COM3 LPTA

01010

FAR e 08

PRI PRI COM3 LPTB

01011

FAR e 08

PRI SEC COM3 LPTB

FER e 0F

FDC UART1 UART2

ll PORT

PTR e 00 80

Power-Down Clocks Option

01100

FAR e 10

PRI COM1 COM2 LPTB

01101

FAR e 11

PRI COM1 COM2 LPTA

01110

FAR e 39

PRI COM3 COM4 LPTA

01111

FAR e 24

PRI COM2 COM3 LPTB

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