PC97338VLJ datasheet(28/221 Pages) NSC

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IRQ3

IRQ4

IRQ5

IRQ6

IRQ7

IRQ9

IRQ10

IRQ11

IRQ12

IRQ15

(Plug and

Play mode)

100

I/O

Group 6

Interrupts Requests 3, 4, 5, 6, 7, 9, 10, 11, 12 and 15. These

signals are used to request an interrupt from the host processor,

when appropriate. These output pins can be configured as totem-

pole or open-drain outputs (see below).

Any of these interrupt request lines may be assigned to any one of

the following: SCC1, SCC2, parallel port, FDC, SIRQI1 signal,

SIRQI2 signal, or SIRQI3 signal. For more details, refer to Sections

2 and 6.

When the parallel port’s interrupt is routed to one of these pins, bit

6 of the PCR determines whether the output signal is totem pole or

open drain. Otherwise, they are totem-pole outputs.

This pin is I/O only when the parallel port’s interrupt is routed to this

pin, ECP is enabled and bit 6 of PCR is 1.The Plug and Play mode

is determined by bit 3 of PNP0.

IRQ5 is multiplexed with ADRATE0.

IRQ12 is multiplexed with DSR2, IRRX2 and IRSL0.

IRQ15 is multiplexed with SIRQI1 and DRQ3.

IRQ3

IRQ4

(Legacy

mode)

100

Group 6

Interrupts 3 and 4. These are active high interrupts associated with

the serial ports. IRQ3 presents the device interrupt request if the

serial channel has been designated as COM2 or COM4. IRQ4

presents the device interrupt request if the serial port is designated

as COM1 or COM3.

The appropriate interrupt is enabled via IER, the associated

Interrupt Enable bit (Modem Control Register (MCR) bit 3), and the

interrupt request is actually triggered when one of the following

events occur: Receiver Error, Receive Data available, Transmitter

Holding Register Empty, or a Modem Status Flag is set.

The interrupt request signal becomes inactive (low) after the

appropriate interrupt service routine is executed, after being

disabled via the IER, or after a Master Reset. Either interrupt can

be disabled and put in TRI-STATE by setting bit 3 of the MCR low.

IRQ5

(Legacy

mode)

I/O

Group 6

Interrupt 5. This active high output signal indicates a parallel port

interrupt request. When enabled, this signal follows the ACK signal

input. When bit 4 in the parallel port Control Register is set and the

parallel port address is designated as shown in Table 11, this

interrupt is enabled. When not enabled this signal is TRI-STATE.

This pin is I/O only when ECP is enabled, and IRQ5 is configured.

IRQ6

(Legacy

mode)

Group 6

Interrupt 6. This active high output signal indicates an interrupt

request upon completion of the execution phase for certain FDC

commands. It also signals when a data transfer is ready during a

non-DMA operation. In PC-AT or Model 30 mode, this signal is

enabled by bit D3 of the DOR. In PS/2 mode, IRQ6 is always

enabled, and bit D3 of the DOR is reserved.

IRQ7

(Legacy

mode)

I/O

Group 6

Interrupt 7. This active high output signal indicates a parallel port

interrupt request. When enabled, this signal follows the ACK signal

input. When bit 4 in the parallel port Control Register is set and the

parallel port address is designated as shown in Table 11, this

interrupt is enabled. When not enabled, this signal is in TRI-STATE.

This pin is I/O only when ECP is enabled, and IRQ7 is configured.

For ECP operation, refer to the interrupt ECP in Section 4.5.5.

Symbol

PQFP

TQFP

I/O and

Group #

Function

PC97338VLJ Datasheet(PDF) 28 Page - National Semiconductor (TI)

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