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PC97338VLJ Datasheet(PDF) 69 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # PC97338VLJ
Description  ACPI 1.0 and PC98/99 Compliant SuperI/O
PDF  221 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC97338VLJ Datasheet(HTML) 69 Page - National Semiconductor (TI)

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3.0 The Digital Floppy Disk
Controller (FDC)
The Floppy Disk Controller (FDC) is suitable for all
PC-AT, EISA, PS/2, and general purpose applica-
tions. DP8473 and N82077 software compatibility is
provided. Key features include a 16-byte FIFO, PS/2
diagnostic register support, perpendicular recording
mode, CMOS disk input and output logic, and a high
performance Digital Data Separator (DDS).
Figure 41shows a functional block diagram of the
FDC. The rest of this Section describes the FDC func-
tions, data transfer, the FDC registers, the phases of
FDC commands, the result phase status registers and
the FDC commands, in that order.
3.1
FDC FUNCTIONS
The Chip is software compatible with the DP8473 and
82077 Floppy Disk Controllers (FDCs). Upon a pow-
er-on reset, the 16-byte FIFO is disabled. Also, the
disk interface output signals are configured as active
push-pull output signals, which are compatible with
both CMOS input signals and open-collector resistor
terminated disk drive input signals. The FIFO can be
enabled with the CONFIGURE command. The FIFO
can be very useful at high data rates, with systems
that have a long DMA bus latency, or with multi-task-
ing systems such as the EISA or MCA bus structures.
The FDC supports all the DP8473 MODE command
features as well as some additional features. These
include control over the enabling of the FIFO for read
and write operations, disabling burst mode for the
FIFO, a bit that will configure the disk interface out-
puts as open-drain output signals, and programmabil-
ity of the DENSEL output signal.
3.1.1
Microprocessor Interface
The FDC interface to the microprocessor consists of
the A9-3, AEN, RD, and WR signals, which access
the chip for read and write operations; the data sig-
nals D7-0; the address lines A2-0, which select the
appropriate register (see Table 35); the IRQ6 signal,
and the DMA interface signals DRQ, DACK, and TC.
It is through this microprocessor interface that the
Floppy Disk Controller (FDC) receives commands,
transfers data, and returns status information.
FIGURE 41. FDC Functional Block Diagram
Internal Control and Data Bus
Interface
Logic
Address
Decoder
DMA
Enable
Logic
Main Status
Register
16-Byte
FIFO
(MSR)
PC8477B
Micro-Engine
and
Timing/Control
Logic
Data Rate
Selection
Register
(DSR)
Configuration
Control
Register
(CCR)
2 KB x 16
Micro-Code
Status
Register A
Status
Register B
Digital Input
Register
(DIR)
Digital Output
Register
(DOR)
Write
Precompen-
Digital
Data
Separator
(DDS)
Disk
Input
and
Output
Logic
DRATE1,0
DENSEL
DIR
DR1
DR23
HDSEL
MTR0
sator
MTR1
STEP
WGATE
WDATA
DSKCHG
DRV2
INDEX
RDATA
TRK0
WP
MSEN1,0
RD
FDC Chip
WR
A2-0
Reset
D7-0
FDC DMA
TC
FDC DMA
Interrupt
FDC Clock
Select
Acknowledge
Request
DR0



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